/*
 * 
 *
 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
 * 
 * Copyright 2007-2020 Broadcom Inc. All rights reserved.
 */
#include <sal/types.h>
#ifndef _WC_ADDRESS_H_
#define _WC_ADDRESS_H_

#define IEEE0BLK_MIICNTL_NAME "IEEE0BLK_MIICNTL"
#define IEEE0BLK_MIICNTL_ADDR  0x00000000

#define IEEE0BLK_MIISTAT_NAME "IEEE0BLK_MIISTAT"
#define IEEE0BLK_MIISTAT_ADDR  0x00000001

#define IEEE0BLK_ID1_NAME "IEEE0BLK_ID1"
#define IEEE0BLK_ID1_ADDR  0x00000002

#define IEEE0BLK_ID2_NAME "IEEE0BLK_ID2"
#define IEEE0BLK_ID2_ADDR  0x00000003

#define IEEE0BLK_AUTONEGADV_NAME "IEEE0BLK_AUTONEGADV"
#define IEEE0BLK_AUTONEGADV_ADDR  0x00000004

#define IEEE0BLK_AUTONEGLPABIL_NAME "IEEE0BLK_AUTONEGLPABIL"
#define IEEE0BLK_AUTONEGLPABIL_ADDR  0x00000005

#define IEEE0BLK_AUTONEGEXP_NAME "IEEE0BLK_AUTONEGEXP"
#define IEEE0BLK_AUTONEGEXP_ADDR  0x00000006

#define IEEE0BLK_AUTONEGNP_NAME "IEEE0BLK_AUTONEGNP"
#define IEEE0BLK_AUTONEGNP_ADDR  0x00000007

#define IEEE0BLK_AUTONEGLPABIL2_NAME "IEEE0BLK_AUTONEGLPABIL2"
#define IEEE0BLK_AUTONEGLPABIL2_ADDR  0x00000008

#define IEEE0BLK_MIIEXTSTAT_NAME "IEEE0BLK_MIIEXTSTAT"
#define IEEE0BLK_MIIEXTSTAT_ADDR  0x0000000f

#define XGXSBLK0_XGXSCONTROL_NAME "XGXSBLK0_XGXSCONTROL"
#define XGXSBLK0_XGXSCONTROL_ADDR  0x00008000

#define XGXSBLK0_XGXSSTATUS_NAME "XGXSBLK0_XGXSSTATUS"
#define XGXSBLK0_XGXSSTATUS_ADDR  0x00008001

#define XGXSBLK0_XGMIIIDLE_NAME "XGXSBLK0_XGMIIIDLE"
#define XGXSBLK0_XGMIIIDLE_ADDR  0x00008002

#define XGXSBLK0_XGMIISYNC_NAME "XGXSBLK0_XGMIISYNC"
#define XGXSBLK0_XGMIISYNC_ADDR  0x00008003

#define XGXSBLK0_XGMIISKIP_NAME "XGXSBLK0_XGMIISKIP"
#define XGXSBLK0_XGMIISKIP_ADDR  0x00008004

#define XGXSBLK0_XGMIISOPEOP_NAME "XGXSBLK0_XGMIISOPEOP"
#define XGXSBLK0_XGMIISOPEOP_ADDR  0x00008005

#define XGXSBLK0_XGMIIALIGN_NAME "XGXSBLK0_XGMIIALIGN"
#define XGXSBLK0_XGMIIALIGN_ADDR  0x00008006

#define XGXSBLK0_XGMIIRCONTROL_NAME "XGXSBLK0_XGMIIRCONTROL"
#define XGXSBLK0_XGMIIRCONTROL_ADDR  0x00008007

#define XGXSBLK0_XGMIITCONTROL_NAME "XGXSBLK0_XGMIITCONTROL"
#define XGXSBLK0_XGMIITCONTROL_ADDR  0x00008008

#define XGXSBLK0_XGMIISWAP_NAME "XGXSBLK0_XGMIISWAP"
#define XGXSBLK0_XGMIISWAP_ADDR  0x00008009

#define XGXSBLK0_LSSLSID_NAME "XGXSBLK0_LSSLSID"
#define XGXSBLK0_LSSLSID_ADDR  0x0000800a

#define XGXSBLK0_LSSTINFO_NAME "XGXSBLK0_LSSTINFO"
#define XGXSBLK0_LSSTINFO_ADDR  0x0000800b

#define XGXSBLK0_LSSRINFO_NAME "XGXSBLK0_LSSRINFO"
#define XGXSBLK0_LSSRINFO_ADDR  0x0000800c

#define XGXSBLK0_MMDSELECT_NAME "XGXSBLK0_MMDSELECT"
#define XGXSBLK0_MMDSELECT_ADDR  0x0000800d

#define XGXSBLK0_MISCCONTROL1_NAME "XGXSBLK0_MISCCONTROL1"
#define XGXSBLK0_MISCCONTROL1_ADDR  0x0000800e

#define XGXSBLK0_BLOCKADDRESS_NAME "XGXSBLK0_BLOCKADDRESS"
#define XGXSBLK0_BLOCKADDRESS_ADDR  0x0000800f

#define XGXSBLK1_DESKEW_NAME "XGXSBLK1_DESKEW"
#define XGXSBLK1_DESKEW_ADDR  0x00008010

#define XGXSBLK1_LINK_NAME "XGXSBLK1_LINK"
#define XGXSBLK1_LINK_ADDR  0x00008011

#define XGXSBLK1_TESTRX_NAME "XGXSBLK1_TESTRX"
#define XGXSBLK1_TESTRX_ADDR  0x00008012

#define XGXSBLK1_TESTTX_NAME "XGXSBLK1_TESTTX"
#define XGXSBLK1_TESTTX_ADDR  0x00008013

#define XGXSBLK1_TESTXG_NAME "XGXSBLK1_TESTXG"
#define XGXSBLK1_TESTXG_ADDR  0x00008014

#define XGXSBLK1_LANECTRL0_NAME "XGXSBLK1_LANECTRL0"
#define XGXSBLK1_LANECTRL0_ADDR  0x00008015

#define XGXSBLK1_LANECTRL1_NAME "XGXSBLK1_LANECTRL1"
#define XGXSBLK1_LANECTRL1_ADDR  0x00008016

#define XGXSBLK1_LANECTRL2_NAME "XGXSBLK1_LANECTRL2"
#define XGXSBLK1_LANECTRL2_ADDR  0x00008017

#define XGXSBLK1_LANECTRL3_NAME "XGXSBLK1_LANECTRL3"
#define XGXSBLK1_LANECTRL3_ADDR  0x00008018

#define XGXSBLK1_LANEPRBS_NAME "XGXSBLK1_LANEPRBS"
#define XGXSBLK1_LANEPRBS_ADDR  0x00008019

#define XGXSBLK1_LANETEST_NAME "XGXSBLK1_LANETEST"
#define XGXSBLK1_LANETEST_ADDR  0x0000801a

#define XGXSBLK1_LSSREVNT_NAME "XGXSBLK1_LSSREVNT"
#define XGXSBLK1_LSSREVNT_ADDR  0x0000801b

#define XGXSBLK1_DSKEVNT_NAME "XGXSBLK1_DSKEVNT"
#define XGXSBLK1_DSKEVNT_ADDR  0x0000801c

#define XGXSBLK1_AERREVNT_NAME "XGXSBLK1_AERREVNT"
#define XGXSBLK1_AERREVNT_ADDR  0x0000801d

#define XGXSBLK1_CKCMPEVNT_NAME "XGXSBLK1_CKCMPEVNT"
#define XGXSBLK1_CKCMPEVNT_ADDR  0x0000801e

#define XGXSBLK1_BLOCKADDRESS_NAME "XGXSBLK1_BLOCKADDRESS"
#define XGXSBLK1_BLOCKADDRESS_ADDR  0x0000801f

#define TXBERT_TXBERTCTRL_NAME "TXBERT_TXBERTCTRL"
#define TXBERT_TXBERTCTRL_ADDR  0x00008020

#define TXBERT_TXBERTSOPEOP_NAME "TXBERT_TXBERTSOPEOP"
#define TXBERT_TXBERTSOPEOP_ADDR  0x00008021

#define TXBERT_TXBERTSIZE0_NAME "TXBERT_TXBERTSIZE0"
#define TXBERT_TXBERTSIZE0_ADDR  0x00008022

#define TXBERT_TXBERTSIZE1_NAME "TXBERT_TXBERTSIZE1"
#define TXBERT_TXBERTSIZE1_ADDR  0x00008023

#define TXBERT_TXBERTSIZE2_NAME "TXBERT_TXBERTSIZE2"
#define TXBERT_TXBERTSIZE2_ADDR  0x00008024

#define TXBERT_TXBERTIPG0_NAME "TXBERT_TXBERTIPG0"
#define TXBERT_TXBERTIPG0_ADDR  0x00008025

#define TXBERT_TXBERTIPG1_NAME "TXBERT_TXBERTIPG1"
#define TXBERT_TXBERTIPG1_ADDR  0x00008026

#define TXBERT_TXBERTBYTEU_NAME "TXBERT_TXBERTBYTEU"
#define TXBERT_TXBERTBYTEU_ADDR  0x00008027

#define TXBERT_TXBERTBYTEL_NAME "TXBERT_TXBERTBYTEL"
#define TXBERT_TXBERTBYTEL_ADDR  0x00008028

#define TXBERT_TXBERTPACKETU_NAME "TXBERT_TXBERTPACKETU"
#define TXBERT_TXBERTPACKETU_ADDR  0x00008029

#define TXBERT_TXBERTPACKETL_NAME "TXBERT_TXBERTPACKETL"
#define TXBERT_TXBERTPACKETL_ADDR  0x0000802a

#define TXBERT_TXBERTCTRL1_NAME "TXBERT_TXBERTCTRL1"
#define TXBERT_TXBERTCTRL1_ADDR  0x0000802b

#define RXBERT_RXBERTCTRL_NAME "RXBERT_RXBERTCTRL"
#define RXBERT_RXBERTCTRL_ADDR  0x00008030

#define RXBERT_RXBERTSOPEOP_NAME "RXBERT_RXBERTSOPEOP"
#define RXBERT_RXBERTSOPEOP_ADDR  0x00008031

#define RXBERT_RXBERTBYTEU_NAME "RXBERT_RXBERTBYTEU"
#define RXBERT_RXBERTBYTEU_ADDR  0x00008037

#define RXBERT_RXBERTBYTEL_NAME "RXBERT_RXBERTBYTEL"
#define RXBERT_RXBERTBYTEL_ADDR  0x00008038

#define RXBERT_RXBERTPACKETU_NAME "RXBERT_RXBERTPACKETU"
#define RXBERT_RXBERTPACKETU_ADDR  0x00008039

#define RXBERT_RXBERTPACKETL_NAME "RXBERT_RXBERTPACKETL"
#define RXBERT_RXBERTPACKETL_ADDR  0x0000803a

#define RXBERT_RXBERTBITERR_NAME "RXBERT_RXBERTBITERR"
#define RXBERT_RXBERTBITERR_ADDR  0x0000803b

#define RXBERT_RXBERTBYTEERR_NAME "RXBERT_RXBERTBYTEERR"
#define RXBERT_RXBERTBYTEERR_ADDR  0x0000803c

#define RXBERT_RXBERTPKTERR_NAME "RXBERT_RXBERTPKTERR"
#define RXBERT_RXBERTPKTERR_ADDR  0x0000803d

#define RXBERT_RXBERTSTATUS_NAME "RXBERT_RXBERTSTATUS"
#define RXBERT_RXBERTSTATUS_ADDR  0x0000803e

#define PLL_ANAPLLSTATUS_NAME "PLL_ANAPLLSTATUS"
#define PLL_ANAPLLSTATUS_ADDR  0x00008050

#define PLL_ANAPLLCONTROL_NAME "PLL_ANAPLLCONTROL"
#define PLL_ANAPLLCONTROL_ADDR  0x00008051

#define PLL_ANAPLLTIMER1_NAME "PLL_ANAPLLTIMER1"
#define PLL_ANAPLLTIMER1_ADDR  0x00008052

#define PLL_ANAPLLTIMER2_NAME "PLL_ANAPLLTIMER2"
#define PLL_ANAPLLTIMER2_ADDR  0x00008053

#define PLL_ANAPLLTIMER3_NAME "PLL_ANAPLLTIMER3"
#define PLL_ANAPLLTIMER3_ADDR  0x00008054

#define PLL_ANACAPCONTROL_NAME "PLL_ANACAPCONTROL"
#define PLL_ANACAPCONTROL_ADDR  0x00008055

#define PLL_ANAFREQDETCNTR_NAME "PLL_ANAFREQDETCNTR"
#define PLL_ANAFREQDETCNTR_ADDR  0x00008057

#define PLL_ANAPLLASTATUS1_NAME "PLL_ANAPLLASTATUS1"
#define PLL_ANAPLLASTATUS1_ADDR  0x00008058

#define PLL_ANAPLLACONTROL0_NAME "PLL_ANAPLLACONTROL0"
#define PLL_ANAPLLACONTROL0_ADDR  0x0000805a

#define PLL_ANAPLLACONTROL1_NAME "PLL_ANAPLLACONTROL1"
#define PLL_ANAPLLACONTROL1_ADDR  0x0000805b

#define PLL_ANAPLLACONTROL2_NAME "PLL_ANAPLLACONTROL2"
#define PLL_ANAPLLACONTROL2_ADDR  0x0000805c

#define PLL_ANAPLLACONTROL3_NAME "PLL_ANAPLLACONTROL3"
#define PLL_ANAPLLACONTROL3_ADDR  0x0000805d

#define PLL_ANAPLLACONTROL4_NAME "PLL_ANAPLLACONTROL4"
#define PLL_ANAPLLACONTROL4_ADDR  0x0000805e

#define TX0_ANATXASTATUS0_NAME "TX0_ANATXASTATUS0"
#define TX0_ANATXASTATUS0_ADDR  0x00008060

#define TX0_ANATXACONTROL0_NAME "TX0_ANATXACONTROL0"
#define TX0_ANATXACONTROL0_ADDR  0x00008061

#define TX0_ANATXMDATA0_NAME "TX0_ANATXMDATA0"
#define TX0_ANATXMDATA0_ADDR  0x00008062

#define TX0_ANATXMDATA1_NAME "TX0_ANATXMDATA1"
#define TX0_ANATXMDATA1_ADDR  0x00008063

#define TX0_ANATXASTATUS1_NAME "TX0_ANATXASTATUS1"
#define TX0_ANATXASTATUS1_ADDR  0x00008064

#define TX0_ANATXACONTROL1_NAME "TX0_ANATXACONTROL1"
#define TX0_ANATXACONTROL1_ADDR  0x00008065

#define TX0_ANATXACONTROL2_NAME "TX0_ANATXACONTROL2"
#define TX0_ANATXACONTROL2_ADDR  0x00008066

#define TX0_TX_DRIVER_NAME "TX0_TX_DRIVER"
#define TX0_TX_DRIVER_ADDR  0x00008067
#ifdef BCM_TRIUMPH3_SUPPORT
#define TX0_ANATXACONTROL6_NAME "TX0_ANATXACONTROL6"
#define TX0_ANATXACONTROL6_ADDR  0x0000806a
#endif
#define TX1_ANATXASTATUS0_NAME "TX1_ANATXASTATUS0"
#define TX1_ANATXASTATUS0_ADDR  0x00008070

#define TX1_ANATXACONTROL0_NAME "TX1_ANATXACONTROL0"
#define TX1_ANATXACONTROL0_ADDR  0x00008071

#define TX1_ANATXMDATA0_NAME "TX1_ANATXMDATA0"
#define TX1_ANATXMDATA0_ADDR  0x00008072

#define TX1_ANATXMDATA1_NAME "TX1_ANATXMDATA1"
#define TX1_ANATXMDATA1_ADDR  0x00008073

#define TX1_ANATXASTATUS1_NAME "TX1_ANATXASTATUS1"
#define TX1_ANATXASTATUS1_ADDR  0x00008074

#define TX1_ANATXACONTROL1_NAME "TX1_ANATXACONTROL1"
#define TX1_ANATXACONTROL1_ADDR  0x00008075

#define TX1_ANATXACONTROL2_NAME "TX1_ANATXACONTROL2"
#define TX1_ANATXACONTROL2_ADDR  0x00008076

#define TX1_TX_DRIVER_NAME "TX1_TX_DRIVER"
#define TX1_TX_DRIVER_ADDR  0x00008077

#define TX2_ANATXASTATUS0_NAME "TX2_ANATXASTATUS0"
#define TX2_ANATXASTATUS0_ADDR  0x00008080

#define TX2_ANATXACONTROL0_NAME "TX2_ANATXACONTROL0"
#define TX2_ANATXACONTROL0_ADDR  0x00008081

#define TX2_ANATXMDATA0_NAME "TX2_ANATXMDATA0"
#define TX2_ANATXMDATA0_ADDR  0x00008082

#define TX2_ANATXMDATA1_NAME "TX2_ANATXMDATA1"
#define TX2_ANATXMDATA1_ADDR  0x00008083

#define TX2_ANATXASTATUS1_NAME "TX2_ANATXASTATUS1"
#define TX2_ANATXASTATUS1_ADDR  0x00008084

#define TX2_ANATXACONTROL1_NAME "TX2_ANATXACONTROL1"
#define TX2_ANATXACONTROL1_ADDR  0x00008085

#define TX2_ANATXACONTROL2_NAME "TX2_ANATXACONTROL2"
#define TX2_ANATXACONTROL2_ADDR  0x00008086

#define TX2_TX_DRIVER_NAME "TX2_TX_DRIVER"
#define TX2_TX_DRIVER_ADDR  0x00008087

#define TX3_ANATXASTATUS0_NAME "TX3_ANATXASTATUS0"
#define TX3_ANATXASTATUS0_ADDR  0x00008090

#define TX3_ANATXACONTROL0_NAME "TX3_ANATXACONTROL0"
#define TX3_ANATXACONTROL0_ADDR  0x00008091

#define TX3_ANATXMDATA0_NAME "TX3_ANATXMDATA0"
#define TX3_ANATXMDATA0_ADDR  0x00008092

#define TX3_ANATXMDATA1_NAME "TX3_ANATXMDATA1"
#define TX3_ANATXMDATA1_ADDR  0x00008093

#define TX3_ANATXASTATUS1_NAME "TX3_ANATXASTATUS1"
#define TX3_ANATXASTATUS1_ADDR  0x00008094

#define TX3_ANATXACONTROL1_NAME "TX3_ANATXACONTROL1"
#define TX3_ANATXACONTROL1_ADDR  0x00008095

#define TX3_ANATXACONTROL2_NAME "TX3_ANATXACONTROL2"
#define TX3_ANATXACONTROL2_ADDR  0x00008096

#define TX3_TX_DRIVER_NAME "TX3_TX_DRIVER"
#define TX3_TX_DRIVER_ADDR  0x00008097

#define TXB_ANATXASTATUS0_NAME "TXB_ANATXASTATUS0"
#define TXB_ANATXASTATUS0_ADDR  0x000080a0

#define TXB_ANATXACONTROL0_NAME "TXB_ANATXACONTROL0"
#define TXB_ANATXACONTROL0_ADDR  0x000080a1

#define TXB_ANATXMDATA0_NAME "TXB_ANATXMDATA0"
#define TXB_ANATXMDATA0_ADDR  0x000080a2

#define TXB_ANATXMDATA1_NAME "TXB_ANATXMDATA1"
#define TXB_ANATXMDATA1_ADDR  0x000080a3

#define TXB_ANATXASTATUS1_NAME "TXB_ANATXASTATUS1"
#define TXB_ANATXASTATUS1_ADDR  0x000080a4

#define TXB_ANATXACONTROL1_NAME "TXB_ANATXACONTROL1"
#define TXB_ANATXACONTROL1_ADDR  0x000080a5

#define TXB_ANATXACONTROL2_NAME "TXB_ANATXACONTROL2"
#define TXB_ANATXACONTROL2_ADDR  0x000080a6

#define TXB_TX_DRIVER_NAME "TXB_TX_DRIVER"
#define TXB_TX_DRIVER_ADDR  0x000080a7

#define RX0_ANARXSTATUS_NAME "RX0_ANARXSTATUS"
#define RX0_ANARXSTATUS_ADDR  0x000080b0

#define RX0_ANARXCONTROL_NAME "RX0_ANARXCONTROL"
#define RX0_ANARXCONTROL_ADDR  0x000080b1

#define RX0_ANARXTEST_NAME "RX0_ANARXTEST"
#define RX0_ANARXTEST_ADDR  0x000080b8

#define RX0_ANARXCONTROL1G_NAME "RX0_ANARXCONTROL1G"
#define RX0_ANARXCONTROL1G_ADDR  0x000080b9

#define RX0_ANARXCONTROLPCI_NAME "RX0_ANARXCONTROLPCI"
#define RX0_ANARXCONTROLPCI_ADDR  0x000080ba

#define RX0_ANARXASTATUS_NAME "RX0_ANARXASTATUS"
#define RX0_ANARXASTATUS_ADDR  0x000080bb

#define RX0_ANARXACONTROL1_NAME "RX0_ANARXACONTROL1"
#define RX0_ANARXACONTROL1_ADDR  0x000080bc

#define RX0_ANARXACONTROL2_NAME "RX0_ANARXACONTROL2"
#define RX0_ANARXACONTROL2_ADDR  0x000080bd

#define RX0_ANARXACONTROL3_NAME "RX0_ANARXACONTROL3"
#define RX0_ANARXACONTROL3_ADDR  0x000080be

#define RX1_ANARXSTATUS_NAME "RX1_ANARXSTATUS"
#define RX1_ANARXSTATUS_ADDR  0x000080c0

#define RX1_ANARXCONTROL_NAME "RX1_ANARXCONTROL"
#define RX1_ANARXCONTROL_ADDR  0x000080c1

#define RX1_ANARXTEST_NAME "RX1_ANARXTEST"
#define RX1_ANARXTEST_ADDR  0x000080c8

#define RX1_ANARXCONTROL1G_NAME "RX1_ANARXCONTROL1G"
#define RX1_ANARXCONTROL1G_ADDR  0x000080c9

#define RX1_ANARXCONTROLPCI_NAME "RX1_ANARXCONTROLPCI"
#define RX1_ANARXCONTROLPCI_ADDR  0x000080ca

#define RX1_ANARXASTATUS_NAME "RX1_ANARXASTATUS"
#define RX1_ANARXASTATUS_ADDR  0x000080cb

#define RX1_ANARXACONTROL1_NAME "RX1_ANARXACONTROL1"
#define RX1_ANARXACONTROL1_ADDR  0x000080cc

#define RX1_ANARXACONTROL2_NAME "RX1_ANARXACONTROL2"
#define RX1_ANARXACONTROL2_ADDR  0x000080cd

#define RX1_ANARXACONTROL3_NAME "RX1_ANARXACONTROL3"
#define RX1_ANARXACONTROL3_ADDR  0x000080ce

#define RX2_ANARXSTATUS_NAME "RX2_ANARXSTATUS"
#define RX2_ANARXSTATUS_ADDR  0x000080d0

#define RX2_ANARXCONTROL_NAME "RX2_ANARXCONTROL"
#define RX2_ANARXCONTROL_ADDR  0x000080d1

#define RX2_ANARXTEST_NAME "RX2_ANARXTEST"
#define RX2_ANARXTEST_ADDR  0x000080d8

#define RX2_ANARXCONTROL1G_NAME "RX2_ANARXCONTROL1G"
#define RX2_ANARXCONTROL1G_ADDR  0x000080d9

#define RX2_ANARXCONTROLPCI_NAME "RX2_ANARXCONTROLPCI"
#define RX2_ANARXCONTROLPCI_ADDR  0x000080da

#define RX2_ANARXASTATUS_NAME "RX2_ANARXASTATUS"
#define RX2_ANARXASTATUS_ADDR  0x000080db

#define RX2_ANARXACONTROL1_NAME "RX2_ANARXACONTROL1"
#define RX2_ANARXACONTROL1_ADDR  0x000080dc

#define RX2_ANARXACONTROL2_NAME "RX2_ANARXACONTROL2"
#define RX2_ANARXACONTROL2_ADDR  0x000080dd

#define RX2_ANARXACONTROL3_NAME "RX2_ANARXACONTROL3"
#define RX2_ANARXACONTROL3_ADDR  0x000080de

#define RX3_ANARXSTATUS_NAME "RX3_ANARXSTATUS"
#define RX3_ANARXSTATUS_ADDR  0x000080e0

#define RX3_ANARXCONTROL_NAME "RX3_ANARXCONTROL"
#define RX3_ANARXCONTROL_ADDR  0x000080e1

#define RX3_ANARXTEST_NAME "RX3_ANARXTEST"
#define RX3_ANARXTEST_ADDR  0x000080e8

#define RX3_ANARXCONTROL1G_NAME "RX3_ANARXCONTROL1G"
#define RX3_ANARXCONTROL1G_ADDR  0x000080e9

#define RX3_ANARXCONTROLPCI_NAME "RX3_ANARXCONTROLPCI"
#define RX3_ANARXCONTROLPCI_ADDR  0x000080ea

#define RX3_ANARXASTATUS_NAME "RX3_ANARXASTATUS"
#define RX3_ANARXASTATUS_ADDR  0x000080eb

#define RX3_ANARXACONTROL1_NAME "RX3_ANARXACONTROL1"
#define RX3_ANARXACONTROL1_ADDR  0x000080ec

#define RX3_ANARXACONTROL2_NAME "RX3_ANARXACONTROL2"
#define RX3_ANARXACONTROL2_ADDR  0x000080ed

#define RX3_ANARXACONTROL3_NAME "RX3_ANARXACONTROL3"
#define RX3_ANARXACONTROL3_ADDR  0x000080ee

#define RXB_ANARXSTATUS_NAME "RXB_ANARXSTATUS"
#define RXB_ANARXSTATUS_ADDR  0x000080f0

#define RXB_ANARXCONTROL_NAME "RXB_ANARXCONTROL"
#define RXB_ANARXCONTROL_ADDR  0x000080f1

#define RXB_ANARXTEST_NAME "RXB_ANARXTEST"
#define RXB_ANARXTEST_ADDR  0x000080f8

#define RXB_ANARXCONTROL1G_NAME "RXB_ANARXCONTROL1G"
#define RXB_ANARXCONTROL1G_ADDR  0x000080f9

#define RXB_ANARXCONTROLPCI_NAME "RXB_ANARXCONTROLPCI"
#define RXB_ANARXCONTROLPCI_ADDR  0x000080fa

#define RXB_ANARXASTATUS_NAME "RXB_ANARXASTATUS"
#define RXB_ANARXASTATUS_ADDR  0x000080fb

#define RXB_ANARXACONTROL1_NAME "RXB_ANARXACONTROL1"
#define RXB_ANARXACONTROL1_ADDR  0x000080fc

#define RXB_ANARXACONTROL2_NAME "RXB_ANARXACONTROL2"
#define RXB_ANARXACONTROL2_ADDR  0x000080fd

#define RXB_ANARXACONTROL3_NAME "RXB_ANARXACONTROL3"
#define RXB_ANARXACONTROL3_ADDR  0x000080fe

#define XGXSBLK2_RXLNSWAP_NAME "XGXSBLK2_RXLNSWAP"
#define XGXSBLK2_RXLNSWAP_ADDR  0x00008100

#define XGXSBLK2_TXLNSWAP_NAME "XGXSBLK2_TXLNSWAP"
#define XGXSBLK2_TXLNSWAP_ADDR  0x00008101

#define XGXSBLK2_QSETLNS01_NAME "XGXSBLK2_QSETLNS01"
#define XGXSBLK2_QSETLNS01_ADDR  0x00008102

#define XGXSBLK2_QSETLNS23_NAME "XGXSBLK2_QSETLNS23"
#define XGXSBLK2_QSETLNS23_ADDR  0x00008103

#define XGXSBLK2_UNICOREMODE10G_NAME "XGXSBLK2_UNICOREMODE10G"
#define XGXSBLK2_UNICOREMODE10G_ADDR  0x00008104

#define XGXSBLK2_INDCOMBCTRL_NAME "XGXSBLK2_INDCOMBCTRL"
#define XGXSBLK2_INDCOMBCTRL_ADDR  0x00008105

#define XGXSBLK2_TESTMODELANE_NAME "XGXSBLK2_TESTMODELANE"
#define XGXSBLK2_TESTMODELANE_ADDR  0x00008106

#define XGXSBLK2_TESTMODECOMBO_NAME "XGXSBLK2_TESTMODECOMBO"
#define XGXSBLK2_TESTMODECOMBO_ADDR  0x00008107

#define XGXSBLK2_TESTMODEMUX_NAME "XGXSBLK2_TESTMODEMUX"
#define XGXSBLK2_TESTMODEMUX_ADDR  0x00008108

#define XGXSBLK2_CX4SIGDETCNT_NAME "XGXSBLK2_CX4SIGDETCNT"
#define XGXSBLK2_CX4SIGDETCNT_ADDR  0x00008109

#define XGXSBLK2_LANERESET_NAME "XGXSBLK2_LANERESET"
#define XGXSBLK2_LANERESET_ADDR  0x0000810a

#define XGXSBLK2_XGXSSTATUS6_NAME "XGXSBLK2_XGXSSTATUS6"
#define XGXSBLK2_XGXSSTATUS6_ADDR  0x0000810b

#define XGXSBLK2_XFICONTROL_NAME "XGXSBLK2_XFICONTROL"
#define XGXSBLK2_XFICONTROL_ADDR  0x0000810c

#define XGXSBLK2_CL73CONTROL7_NAME "XGXSBLK2_CL73CONTROL7"
#define XGXSBLK2_CL73CONTROL7_ADDR  0x0000810d

#define XGXSBLK2_CL73CONTROL8_NAME "XGXSBLK2_CL73CONTROL8"
#define XGXSBLK2_CL73CONTROL8_ADDR  0x0000810e

#define XGXSBLK3_LOCALSTATUS_NAME "XGXSBLK3_LOCALSTATUS"
#define XGXSBLK3_LOCALSTATUS_ADDR  0x00008110

#define XGXSBLK3_LOCALCONTROL0_NAME "XGXSBLK3_LOCALCONTROL0"
#define XGXSBLK3_LOCALCONTROL0_ADDR  0x00008111

#define XGXSBLK3_LOCALCONTROL1_NAME "XGXSBLK3_LOCALCONTROL1"
#define XGXSBLK3_LOCALCONTROL1_ADDR  0x00008112

#define XGXSBLK3_REMOTEWRITE03_NAME "XGXSBLK3_REMOTEWRITE03"
#define XGXSBLK3_REMOTEWRITE03_ADDR  0x00008113

#define XGXSBLK3_REMOTEWRITE12_NAME "XGXSBLK3_REMOTEWRITE12"
#define XGXSBLK3_REMOTEWRITE12_ADDR  0x00008114

#define XGXSBLK3_REMOTEREAD12_NAME "XGXSBLK3_REMOTEREAD12"
#define XGXSBLK3_REMOTEREAD12_ADDR  0x00008115

#define XGXSBLK3_REMOTEREADX3_NAME "XGXSBLK3_REMOTEREADX3"
#define XGXSBLK3_REMOTEREADX3_ADDR  0x00008116

#define XGXSBLK3_RX_INBANDMDIOSTAT_NAME "XGXSBLK3_RX_INBANDMDIOSTAT"
#define XGXSBLK3_RX_INBANDMDIOSTAT_ADDR  0x00008117

#define XGXSBLK3_LOCALIAC_NAME "XGXSBLK3_LOCALIAC"
#define XGXSBLK3_LOCALIAC_ADDR  0x00008118

#define XGXSBLK3_REMOTEIACN_NAME "XGXSBLK3_REMOTEIACN"
#define XGXSBLK3_REMOTEIACN_ADDR  0x00008119

#define XGXSBLK4_MISCRXSTATUS_NAME "XGXSBLK4_MISCRXSTATUS"
#define XGXSBLK4_MISCRXSTATUS_ADDR  0x00008120

#define XGXSBLK4_XGXSSTATUS0_NAME "XGXSBLK4_XGXSSTATUS0"
#define XGXSBLK4_XGXSSTATUS0_ADDR  0x00008121

#define XGXSBLK4_XGXSSTATUS1_NAME "XGXSBLK4_XGXSSTATUS1"
#define XGXSBLK4_XGXSSTATUS1_ADDR  0x00008122

#define XGXSBLK4_XGXSSTATUS2_NAME "XGXSBLK4_XGXSSTATUS2"
#define XGXSBLK4_XGXSSTATUS2_ADDR  0x00008123

#define XGXSBLK4_STATUS1000X1_NAME "XGXSBLK4_STATUS1000X1"
#define XGXSBLK4_STATUS1000X1_ADDR  0x00008124

#define XGXSBLK4_STATUS1000X2_NAME "XGXSBLK4_STATUS1000X2"
#define XGXSBLK4_STATUS1000X2_ADDR  0x00008125

#define XGXSBLK4_STATUS1000X3_NAME "XGXSBLK4_STATUS1000X3"
#define XGXSBLK4_STATUS1000X3_ADDR  0x00008126

#define XGXSBLK4_TPOUT_1_NAME "XGXSBLK4_TPOUT_1"
#define XGXSBLK4_TPOUT_1_ADDR  0x00008127

#define XGXSBLK4_TPOUT_2_NAME "XGXSBLK4_TPOUT_2"
#define XGXSBLK4_TPOUT_2_ADDR  0x00008128

#define XGXSBLK4_XGXSSTATUS3_NAME "XGXSBLK4_XGXSSTATUS3"
#define XGXSBLK4_XGXSSTATUS3_ADDR  0x00008129

#define XGXSBLK4_X2500STATUS1_NAME "XGXSBLK4_X2500STATUS1"
#define XGXSBLK4_X2500STATUS1_ADDR  0x0000812a

#define XGXSBLK4_TOPANSTATUS1_NAME "XGXSBLK4_TOPANSTATUS1"
#define XGXSBLK4_TOPANSTATUS1_ADDR  0x0000812b

#define XGXSBLK4_LP_UP1_NAME "XGXSBLK4_LP_UP1"
#define XGXSBLK4_LP_UP1_ADDR  0x0000812c

#define XGXSBLK4_LP_UP2_NAME "XGXSBLK4_LP_UP2"
#define XGXSBLK4_LP_UP2_ADDR  0x0000812d

#define XGXSBLK4_LP_UP3_NAME "XGXSBLK4_LP_UP3"
#define XGXSBLK4_LP_UP3_ADDR  0x0000812e

#define XGXSBLK5_PARDET10GSTATUS_NAME "XGXSBLK5_PARDET10GSTATUS"
#define XGXSBLK5_PARDET10GSTATUS_ADDR  0x00008130

#define XGXSBLK5_PARDET10GCONTROL_NAME "XGXSBLK5_PARDET10GCONTROL"
#define XGXSBLK5_PARDET10GCONTROL_ADDR  0x00008131

#define XGXSBLK5_PARDET10GSIGDET_NAME "XGXSBLK5_PARDET10GSIGDET"
#define XGXSBLK5_PARDET10GSIGDET_ADDR  0x00008132

#define XGXSBLK5_PARDET10GLINK_NAME "XGXSBLK5_PARDET10GLINK"
#define XGXSBLK5_PARDET10GLINK_ADDR  0x00008133

#define XGXSBLK5_PARDET10GLOSTLINK_NAME "XGXSBLK5_PARDET10GLOSTLINK"
#define XGXSBLK5_PARDET10GLOSTLINK_ADDR  0x00008134

#define XGXSBLK5_CL73CONTROL1_NAME "XGXSBLK5_CL73CONTROL1"
#define XGXSBLK5_CL73CONTROL1_ADDR  0x00008135

#define XGXSBLK5_CL73CONTROL2_NAME "XGXSBLK5_CL73CONTROL2"
#define XGXSBLK5_CL73CONTROL2_ADDR  0x00008136

#define XGXSBLK5_CL73CONTROL3_NAME "XGXSBLK5_CL73CONTROL3"
#define XGXSBLK5_CL73CONTROL3_ADDR  0x00008137

#define XGXSBLK5_CL73CONTROL4_NAME "XGXSBLK5_CL73CONTROL4"
#define XGXSBLK5_CL73CONTROL4_ADDR  0x00008138

#define XGXSBLK5_CL73CONTROL5_NAME "XGXSBLK5_CL73CONTROL5"
#define XGXSBLK5_CL73CONTROL5_ADDR  0x00008139

#define XGXSBLK5_CL73CONTROL6_NAME "XGXSBLK5_CL73CONTROL6"
#define XGXSBLK5_CL73CONTROL6_ADDR  0x0000813a

#define XGXSBLK5_CL73DMETMRS_NAME "XGXSBLK5_CL73DMETMRS"
#define XGXSBLK5_CL73DMETMRS_ADDR  0x0000813b

#define XGXSBLK5_XGXSSTATUS4_NAME "XGXSBLK5_XGXSSTATUS4"
#define XGXSBLK5_XGXSSTATUS4_ADDR  0x0000813c

#define XGXSBLK5_XGXSSTATUS5_NAME "XGXSBLK5_XGXSSTATUS5"
#define XGXSBLK5_XGXSSTATUS5_ADDR  0x0000813d

#define XGXSBLK5_PARDET10GCONTROL2_NAME "XGXSBLK5_PARDET10GCONTROL2"
#define XGXSBLK5_PARDET10GCONTROL2_ADDR  0x0000813e

#define XGXSBLK6_XGXSX2CONTROL1_NAME "XGXSBLK6_XGXSX2CONTROL1"
#define XGXSBLK6_XGXSX2CONTROL1_ADDR  0x00008140

#define XGXSBLK6_XGXSX2CONTROL2_NAME "XGXSBLK6_XGXSX2CONTROL2"
#define XGXSBLK6_XGXSX2CONTROL2_ADDR  0x00008141

#define XGXSBLK6_XGXSX2TEST1_NAME "XGXSBLK6_XGXSX2TEST1"
#define XGXSBLK6_XGXSX2TEST1_ADDR  0x00008143

#define XGXSBLK6_XGXSX2STATUS1_NAME "XGXSBLK6_XGXSX2STATUS1"
#define XGXSBLK6_XGXSX2STATUS1_ADDR  0x00008144

#define XGXSBLK6_BPMCONTROL_NAME "XGXSBLK6_BPMCONTROL"
#define XGXSBLK6_BPMCONTROL_ADDR  0x00008147

#define XGXSBLK6_BPMSTATUS_NAME "XGXSBLK6_BPMSTATUS"
#define XGXSBLK6_BPMSTATUS_ADDR  0x00008148

#define XGXSBLK6_BPM10GTIMER_NAME "XGXSBLK6_BPM10GTIMER"
#define XGXSBLK6_BPM10GTIMER_ADDR  0x00008149

#define XGXSBLK6_BPM1GTIMER_NAME "XGXSBLK6_BPM1GTIMER"
#define XGXSBLK6_BPM1GTIMER_ADDR  0x0000814a

#define XGXSBLK6_BPMTXDISTIMER_NAME "XGXSBLK6_BPMTXDISTIMER"
#define XGXSBLK6_BPMTXDISTIMER_ADDR  0x0000814b

#define XGXSBLK7_EEECONTROL_NAME "XGXSBLK7_EEECONTROL"
#define XGXSBLK7_EEECONTROL_ADDR  0x00008150

#define XGXSBLK7_EEESTATUS_NAME "XGXSBLK7_EEESTATUS"
#define XGXSBLK7_EEESTATUS_ADDR  0x00008151

#define XGXSBLK7_XGMIILPI_NAME "XGXSBLK7_XGMIILPI"
#define XGXSBLK7_XGMIILPI_ADDR  0x00008152

#define XGXSBLK7_LPILANE13_NAME "XGXSBLK7_LPILANE13"
#define XGXSBLK7_LPILANE13_ADDR  0x00008153

#define XGXSBLK7_QRSVD1_NAME "XGXSBLK7_QRSVD1"
#define XGXSBLK7_QRSVD1_ADDR  0x00008154

#define XGXSBLK7_QRSVD23_NAME "XGXSBLK7_QRSVD23"
#define XGXSBLK7_QRSVD23_ADDR  0x00008155

#define XGXSBLK7_QRSVDSWAP_NAME "XGXSBLK7_QRSVDSWAP"
#define XGXSBLK7_QRSVDSWAP_ADDR  0x00008156

#define XGXSBLK7_QRSVDSTATUS_NAME "XGXSBLK7_QRSVDSTATUS"
#define XGXSBLK7_QRSVDSTATUS_ADDR  0x00008157

#define XGXSBLK7_CL48_TX_LPI_SM_NAME "XGXSBLK7_CL48_TX_LPI_SM"
#define XGXSBLK7_CL48_TX_LPI_SM_ADDR  0x00008158

#define XGXSBLK7_CL48_RX_LPI_SM_NAME "XGXSBLK7_CL48_RX_LPI_SM"
#define XGXSBLK7_CL48_RX_LPI_SM_ADDR  0x00008159

#define XGXSBLK7_FIFO_CTRL_NAME "XGXSBLK7_FIFO_CTRL"
#define XGXSBLK7_FIFO_CTRL_ADDR  0x0000815d

#define XGXSBLK7_FIFO_STATUS_NAME "XGXSBLK7_FIFO_STATUS"
#define XGXSBLK7_FIFO_STATUS_ADDR  0x0000815e

#define XGXSBLK8_CL73CONTROL7_NAME "XGXSBLK8_CL73CONTROL7"
#define XGXSBLK8_CL73CONTROL7_ADDR  0x00008160

#define XGXSBLK8_CL73CONTROL8_NAME "XGXSBLK8_CL73CONTROL8"
#define XGXSBLK8_CL73CONTROL8_ADDR  0x00008161

#define XGXSBLK8_CL73CONTROL9_NAME "XGXSBLK8_CL73CONTROL9"
#define XGXSBLK8_CL73CONTROL9_ADDR  0x00008162

#define XGXSBLK8_CL73CONTROL10_NAME "XGXSBLK8_CL73CONTROL10"
#define XGXSBLK8_CL73CONTROL10_ADDR  0x00008163

#define XGXSBLK8_TX_PI_CONTROL1_NAME "XGXSBLK8_TX_PI_CONTROL1"
#define XGXSBLK8_TX_PI_CONTROL1_ADDR  0x00008164

#define XGXSBLK8_TX_PI_CONTROL2_NAME "XGXSBLK8_TX_PI_CONTROL2"
#define XGXSBLK8_TX_PI_CONTROL2_ADDR  0x00008165

#define XGXSBLK8_TX_PI_CONTROL3_NAME "XGXSBLK8_TX_PI_CONTROL3"
#define XGXSBLK8_TX_PI_CONTROL3_ADDR  0x00008166

#define XGXSBLK8_TX_PI_STATUS1_NAME "XGXSBLK8_TX_PI_STATUS1"
#define XGXSBLK8_TX_PI_STATUS1_ADDR  0x00008167

#define XGXSBLK8_TX_PI_STATUS2_NAME "XGXSBLK8_TX_PI_STATUS2"
#define XGXSBLK8_TX_PI_STATUS2_ADDR  0x00008168

#define XGXSBLK8_TXLNSWAP1_NAME "XGXSBLK8_TXLNSWAP1"
#define XGXSBLK8_TXLNSWAP1_ADDR  0x00008169

#define XGXSBLK8_TXLNSWAP2_NAME "XGXSBLK8_TXLNSWAP2"
#define XGXSBLK8_TXLNSWAP2_ADDR  0x0000816a

#define XGXSBLK8_RXLNSWAP1_NAME "XGXSBLK8_RXLNSWAP1"
#define XGXSBLK8_RXLNSWAP1_ADDR  0x0000816b

#define XGXSBLK8_RXLNSWAP2_NAME "XGXSBLK8_RXLNSWAP2"
#define XGXSBLK8_RXLNSWAP2_ADDR  0x0000816c

#define XGXSBLK8_TEMP_SENSOR1_NAME "XGXSBLK8_TEMP_SENSOR1"
#define XGXSBLK8_TEMP_SENSOR1_ADDR  0x0000816d

#define XGXSBLK8_TEMP_SENSOR2_NAME "XGXSBLK8_TEMP_SENSOR2"
#define XGXSBLK8_TEMP_SENSOR2_ADDR  0x0000816e

#define XGXSBLK10_TX_PI_CONTROL4_NAME "XGXSBLK10_TX_PI_CONTROL4"
#define XGXSBLK10_TX_PI_CONTROL4_ADDR  0x00008190

#define XGXSBLK10_XFI_AFE_CTL1_NAME "XGXSBLK10_XFI_AFE_CTL1"
#define XGXSBLK10_XFI_AFE_CTL1_ADDR  0x00008191

#define XGXSBLK10_XFI_AFE_CTL2_NAME "XGXSBLK10_XFI_AFE_CTL2"
#define XGXSBLK10_XFI_AFE_CTL2_ADDR  0x00008192

#define XGXSBLK10_XFI_AFE_ACJVAL_NAME "XGXSBLK10_XFI_AFE_ACJVAL"
#define XGXSBLK10_XFI_AFE_ACJVAL_ADDR  0x00008193

#define XGXSBLK10_TX_PI_STATUS3_NAME "XGXSBLK10_TX_PI_STATUS3"
#define XGXSBLK10_TX_PI_STATUS3_ADDR  0x00008194

#define XGXSBLK10_TX_PI_STATUS4_NAME "XGXSBLK10_TX_PI_STATUS4"
#define XGXSBLK10_TX_PI_STATUS4_ADDR  0x00008195

#define XGXSBLK10_TX_PI_CONTROL5_NAME "XGXSBLK10_TX_PI_CONTROL5"
#define XGXSBLK10_TX_PI_CONTROL5_ADDR  0x00008196

#define GP2_REG_GP2_0_NAME "GP2_REG_GP2_0"
#define GP2_REG_GP2_0_ADDR  0x000081d0

#define GP2_REG_GP2_1_NAME "GP2_REG_GP2_1"
#define GP2_REG_GP2_1_ADDR  0x000081d1

#define GP2_REG_GP2_2_NAME "GP2_REG_GP2_2"
#define GP2_REG_GP2_2_ADDR  0x000081d2

#define GP2_REG_GP2_3_NAME "GP2_REG_GP2_3"
#define GP2_REG_GP2_3_ADDR  0x000081d3

#define GP2_REG_GP2_4_NAME "GP2_REG_GP2_4"
#define GP2_REG_GP2_4_ADDR  0x000081d4

#define GP2_REG_GP2_5_NAME "GP2_REG_GP2_5"
#define GP2_REG_GP2_5_ADDR  0x000081d5

#define GP2_REG_GP2_6_NAME "GP2_REG_GP2_6"
#define GP2_REG_GP2_6_ADDR  0x000081d6

#define GP2_REG_GP2_7_NAME "GP2_REG_GP2_7"
#define GP2_REG_GP2_7_ADDR  0x000081d7

#define GP2_REG_GP2_8_NAME "GP2_REG_GP2_8"
#define GP2_REG_GP2_8_ADDR  0x000081d8

#define GP2_REG_GP2_9_NAME "GP2_REG_GP2_9"
#define GP2_REG_GP2_9_ADDR  0x000081d9

#define GP2_REG_GP2_A_NAME "GP2_REG_GP2_A"
#define GP2_REG_GP2_A_ADDR  0x000081da

#define GP2_REG_GP2_B_NAME "GP2_REG_GP2_B"
#define GP2_REG_GP2_B_ADDR  0x000081db

#define GP2_REG_GP2_C_NAME "GP2_REG_GP2_C"
#define GP2_REG_GP2_C_ADDR  0x000081dc

#define GP2_REG_GP2_D_NAME "GP2_REG_GP2_D"
#define GP2_REG_GP2_D_ADDR  0x000081dd

#define GP2_REG_GP2_E_NAME "GP2_REG_GP2_E"
#define GP2_REG_GP2_E_ADDR  0x000081de

#define UC_DEBUG_B0_REG0_NAME "UC_DEBUG_B0_REG0"
#define UC_DEBUG_B0_REG0_ADDR  0x000081e0

#define UC_DEBUG_B0_REG1_NAME "UC_DEBUG_B0_REG1"
#define UC_DEBUG_B0_REG1_ADDR  0x000081e1

#define UC_DEBUG_B0_REG2_NAME "UC_DEBUG_B0_REG2"
#define UC_DEBUG_B0_REG2_ADDR  0x000081e2

#define UC_DEBUG_B0_REG3_NAME "UC_DEBUG_B0_REG3"
#define UC_DEBUG_B0_REG3_ADDR  0x000081e3

#define UC_DEBUG_B0_REG4_NAME "UC_DEBUG_B0_REG4"
#define UC_DEBUG_B0_REG4_ADDR  0x000081e4

#define UC_DEBUG_B0_REG5_NAME "UC_DEBUG_B0_REG5"
#define UC_DEBUG_B0_REG5_ADDR  0x000081e5

#define UC_DEBUG_B0_REG6_NAME "UC_DEBUG_B0_REG6"
#define UC_DEBUG_B0_REG6_ADDR  0x000081e6

#define UC_DEBUG_B0_REG7_NAME "UC_DEBUG_B0_REG7"
#define UC_DEBUG_B0_REG7_ADDR  0x000081e7

#define UC_DEBUG_B0_REG8_NAME "UC_DEBUG_B0_REG8"
#define UC_DEBUG_B0_REG8_ADDR  0x000081e8

#define UC_DEBUG_B0_REG9_NAME "UC_DEBUG_B0_REG9"
#define UC_DEBUG_B0_REG9_ADDR  0x000081e9

#define UC_DEBUG_B0_REGA_NAME "UC_DEBUG_B0_REGA"
#define UC_DEBUG_B0_REGA_ADDR  0x000081ea

#define UC_DEBUG_B0_REGB_NAME "UC_DEBUG_B0_REGB"
#define UC_DEBUG_B0_REGB_ADDR  0x000081eb

#define UC_DEBUG_B0_REGC_NAME "UC_DEBUG_B0_REGC"
#define UC_DEBUG_B0_REGC_ADDR  0x000081ec

#define UC_DEBUG_B0_REGD_NAME "UC_DEBUG_B0_REGD"
#define UC_DEBUG_B0_REGD_ADDR  0x000081ed

#define UC_DEBUG_B0_REGE_NAME "UC_DEBUG_B0_REGE"
#define UC_DEBUG_B0_REGE_ADDR  0x000081ee

#define UC_DEBUG_B1_REG0_NAME "UC_DEBUG_B1_REG0"
#define UC_DEBUG_B1_REG0_ADDR  0x000081f0

#define UC_DEBUG_B1_REG1_NAME "UC_DEBUG_B1_REG1"
#define UC_DEBUG_B1_REG1_ADDR  0x000081f1

#define UC_DEBUG_B1_REG2_NAME "UC_DEBUG_B1_REG2"
#define UC_DEBUG_B1_REG2_ADDR  0x000081f2

#define UC_DEBUG_B1_REG3_NAME "UC_DEBUG_B1_REG3"
#define UC_DEBUG_B1_REG3_ADDR  0x000081f3

#define UC_DEBUG_B1_REG4_NAME "UC_DEBUG_B1_REG4"
#define UC_DEBUG_B1_REG4_ADDR  0x000081f4

#define UC_DEBUG_B1_REG5_NAME "UC_DEBUG_B1_REG5"
#define UC_DEBUG_B1_REG5_ADDR  0x000081f5

#define UC_DEBUG_B1_REG6_NAME "UC_DEBUG_B1_REG6"
#define UC_DEBUG_B1_REG6_ADDR  0x000081f6

#define UC_DEBUG_B1_REG7_NAME "UC_DEBUG_B1_REG7"
#define UC_DEBUG_B1_REG7_ADDR  0x000081f7

#define UC_DEBUG_B1_REG8_NAME "UC_DEBUG_B1_REG8"
#define UC_DEBUG_B1_REG8_ADDR  0x000081f8

#define UC_DEBUG_B1_REG9_NAME "UC_DEBUG_B1_REG9"
#define UC_DEBUG_B1_REG9_ADDR  0x000081f9

#define UC_DEBUG_B1_REGA_NAME "UC_DEBUG_B1_REGA"
#define UC_DEBUG_B1_REGA_ADDR  0x000081fa

#define UC_DEBUG_B1_REGB_NAME "UC_DEBUG_B1_REGB"
#define UC_DEBUG_B1_REGB_ADDR  0x000081fb

#define UC_DEBUG_B1_REGC_NAME "UC_DEBUG_B1_REGC"
#define UC_DEBUG_B1_REGC_ADDR  0x000081fc

#define UC_DEBUG_B1_REGD_NAME "UC_DEBUG_B1_REGD"
#define UC_DEBUG_B1_REGD_ADDR  0x000081fd

#define UC_DEBUG_B1_REGE_NAME "UC_DEBUG_B1_REGE"
#define UC_DEBUG_B1_REGE_ADDR  0x000081fe

#define DSC1B0_CDR_CTRL0_NAME "DSC1B0_CDR_CTRL0"
#define DSC1B0_CDR_CTRL0_ADDR  0x00008200

#define DSC1B0_CDR_CTRL1_NAME "DSC1B0_CDR_CTRL1"
#define DSC1B0_CDR_CTRL1_ADDR  0x00008201

#define DSC1B0_CDR_CTRL2_NAME "DSC1B0_CDR_CTRL2"
#define DSC1B0_CDR_CTRL2_ADDR  0x00008202

#define DSC1B0_PI_CTRL0_NAME "DSC1B0_PI_CTRL0"
#define DSC1B0_PI_CTRL0_ADDR  0x00008203

#define DSC1B0_PI_CTRL1_NAME "DSC1B0_PI_CTRL1"
#define DSC1B0_PI_CTRL1_ADDR  0x00008204

#define DSC1B0_DFE_VGA_CTRL0_NAME "DSC1B0_DFE_VGA_CTRL0"
#define DSC1B0_DFE_VGA_CTRL0_ADDR  0x00008205

#define DSC1B0_DFE_VGA_CTRL1_NAME "DSC1B0_DFE_VGA_CTRL1"
#define DSC1B0_DFE_VGA_CTRL1_ADDR  0x00008206

#define DSC1B0_DFE_VGA_CTRL2_NAME "DSC1B0_DFE_VGA_CTRL2"
#define DSC1B0_DFE_VGA_CTRL2_ADDR  0x00008207

#define DSC1B0_DFE_VGA_CTRL3_NAME "DSC1B0_DFE_VGA_CTRL3"
#define DSC1B0_DFE_VGA_CTRL3_ADDR  0x00008208

#define DSC1B0_DFE_VGA_CTRL4_NAME "DSC1B0_DFE_VGA_CTRL4"
#define DSC1B0_DFE_VGA_CTRL4_ADDR  0x00008209

#define DSC1B0_DFE_VGA_CTRL5_NAME "DSC1B0_DFE_VGA_CTRL5"
#define DSC1B0_DFE_VGA_CTRL5_ADDR  0x0000820a

#define DSC1B0_DFE_VGA_CTRL6_NAME "DSC1B0_DFE_VGA_CTRL6"
#define DSC1B0_DFE_VGA_CTRL6_ADDR  0x0000820b

#define DSC1B0_DFE_VGA_CTRL7_NAME "DSC1B0_DFE_VGA_CTRL7"
#define DSC1B0_DFE_VGA_CTRL7_ADDR  0x0000820c

#define DSC1B0_DSC_DIAG_CTRL0_NAME "DSC1B0_DSC_DIAG_CTRL0"
#define DSC1B0_DSC_DIAG_CTRL0_ADDR  0x0000820d

#define DSC1B0_UC_CTRL_NAME "DSC1B0_UC_CTRL"
#define DSC1B0_UC_CTRL_ADDR  0x0000820e

#define DSC2B0_ACQ_SM_CTRL0_NAME "DSC2B0_ACQ_SM_CTRL0"
#define DSC2B0_ACQ_SM_CTRL0_ADDR  0x00008210

#define DSC2B0_ACQ_SM_CTRL1_NAME "DSC2B0_ACQ_SM_CTRL1"
#define DSC2B0_ACQ_SM_CTRL1_ADDR  0x00008211

#define DSC2B0_ACQ_SM_CTRL2_NAME "DSC2B0_ACQ_SM_CTRL2"
#define DSC2B0_ACQ_SM_CTRL2_ADDR  0x00008212

#define DSC2B0_ACQ_SM_CTRL3_NAME "DSC2B0_ACQ_SM_CTRL3"
#define DSC2B0_ACQ_SM_CTRL3_ADDR  0x00008213

#define DSC2B0_ACQ_SM_CTRL4_NAME "DSC2B0_ACQ_SM_CTRL4"
#define DSC2B0_ACQ_SM_CTRL4_ADDR  0x00008214

#define DSC2B0_ACQ_SM_CTRL5_NAME "DSC2B0_ACQ_SM_CTRL5"
#define DSC2B0_ACQ_SM_CTRL5_ADDR  0x00008215

#define DSC2B0_ACQ_SM_CTRL6_NAME "DSC2B0_ACQ_SM_CTRL6"
#define DSC2B0_ACQ_SM_CTRL6_ADDR  0x00008216

#define DSC2B0_ACQ_SM_CTRL7_NAME "DSC2B0_ACQ_SM_CTRL7"
#define DSC2B0_ACQ_SM_CTRL7_ADDR  0x00008217

#define DSC2B0_ACQ_SM_CTRL8_NAME "DSC2B0_ACQ_SM_CTRL8"
#define DSC2B0_ACQ_SM_CTRL8_ADDR  0x00008218

#define DSC2B0_DSC_ANA_CTRL0_NAME "DSC2B0_DSC_ANA_CTRL0"
#define DSC2B0_DSC_ANA_CTRL0_ADDR  0x00008219

#define DSC2B0_DSC_ANA_CTRL1_NAME "DSC2B0_DSC_ANA_CTRL1"
#define DSC2B0_DSC_ANA_CTRL1_ADDR  0x0000821a

#define DSC2B0_DSC_ANA_CTRL2_NAME "DSC2B0_DSC_ANA_CTRL2"
#define DSC2B0_DSC_ANA_CTRL2_ADDR  0x0000821b

#define DSC2B0_DSC_ANA_CTRL3_NAME "DSC2B0_DSC_ANA_CTRL3"
#define DSC2B0_DSC_ANA_CTRL3_ADDR  0x0000821c

#define DSC2B0_DSC_ANA_CTRL4_NAME "DSC2B0_DSC_ANA_CTRL4"
#define DSC2B0_DSC_ANA_CTRL4_ADDR  0x0000821d

#define DSC2B0_DSC_MISC_CTRL0_NAME "DSC2B0_DSC_MISC_CTRL0"
#define DSC2B0_DSC_MISC_CTRL0_ADDR  0x0000821e

#define DSC3B0_CDR_STATUS0_NAME "DSC3B0_CDR_STATUS0"
#define DSC3B0_CDR_STATUS0_ADDR  0x00008220

#define DSC3B0_CDR_STATUS1_NAME "DSC3B0_CDR_STATUS1"
#define DSC3B0_CDR_STATUS1_ADDR  0x00008221

#define DSC3B0_CDR_STATUS2_NAME "DSC3B0_CDR_STATUS2"
#define DSC3B0_CDR_STATUS2_ADDR  0x00008222

#define DSC3B0_PI_STATUS0_NAME "DSC3B0_PI_STATUS0"
#define DSC3B0_PI_STATUS0_ADDR  0x00008223

#define DSC3B0_PI_STATUS1_NAME "DSC3B0_PI_STATUS1"
#define DSC3B0_PI_STATUS1_ADDR  0x00008224

#define DSC3B0_DFE_VGA_STATUS0_NAME "DSC3B0_DFE_VGA_STATUS0"
#define DSC3B0_DFE_VGA_STATUS0_ADDR  0x00008225

#define DSC3B0_DFE_VGA_STATUS1_NAME "DSC3B0_DFE_VGA_STATUS1"
#define DSC3B0_DFE_VGA_STATUS1_ADDR  0x00008226

#define DSC3B0_DFE_VGA_STATUS2_NAME "DSC3B0_DFE_VGA_STATUS2"
#define DSC3B0_DFE_VGA_STATUS2_ADDR  0x00008227

#define DSC3B0_DFE_VGA_STATUS3_NAME "DSC3B0_DFE_VGA_STATUS3"
#define DSC3B0_DFE_VGA_STATUS3_ADDR  0x00008228

#define DSC3B0_ACQ_SM_STATUS0_NAME "DSC3B0_ACQ_SM_STATUS0"
#define DSC3B0_ACQ_SM_STATUS0_ADDR  0x00008229

#define DSC3B0_ACQ_SM_STATUS1_NAME "DSC3B0_ACQ_SM_STATUS1"
#define DSC3B0_ACQ_SM_STATUS1_ADDR  0x0000822a

#define DSC3B0_ANA_STATUS0_NAME "DSC3B0_ANA_STATUS0"
#define DSC3B0_ANA_STATUS0_ADDR  0x0000822b

#define DSC3B0_ANA_STATUS1_NAME "DSC3B0_ANA_STATUS1"
#define DSC3B0_ANA_STATUS1_ADDR  0x0000822c

#define DSC3B0_ANA_STATUS2_NAME "DSC3B0_ANA_STATUS2"
#define DSC3B0_ANA_STATUS2_ADDR  0x0000822d

#define DSC3B0_ANA_STATUS3_NAME "DSC3B0_ANA_STATUS3"
#define DSC3B0_ANA_STATUS3_ADDR  0x0000822e

#define DSC4B0_TUNING_SM_CTRL0_NAME "DSC4B0_TUNING_SM_CTRL0"
#define DSC4B0_TUNING_SM_CTRL0_ADDR  0x00008230

#define DSC4B0_TUNING_SM_CTRL1_NAME "DSC4B0_TUNING_SM_CTRL1"
#define DSC4B0_TUNING_SM_CTRL1_ADDR  0x00008231

#define DSC4B0_TUNING_SM_CTRL2_NAME "DSC4B0_TUNING_SM_CTRL2"
#define DSC4B0_TUNING_SM_CTRL2_ADDR  0x00008232

#define DSC4B0_TUNING_SM_CTRL3_NAME "DSC4B0_TUNING_SM_CTRL3"
#define DSC4B0_TUNING_SM_CTRL3_ADDR  0x00008233

#define DSC4B0_TUNING_SM_CTRL4_NAME "DSC4B0_TUNING_SM_CTRL4"
#define DSC4B0_TUNING_SM_CTRL4_ADDR  0x00008234

#define DSC4B0_TUNING_SM_CTRL5_NAME "DSC4B0_TUNING_SM_CTRL5"
#define DSC4B0_TUNING_SM_CTRL5_ADDR  0x00008235

#define DSC4B0_TUNING_SM_CTRL6_NAME "DSC4B0_TUNING_SM_CTRL6"
#define DSC4B0_TUNING_SM_CTRL6_ADDR  0x00008236

#define DSC4B0_TUNING_SM_CTRL7_NAME "DSC4B0_TUNING_SM_CTRL7"
#define DSC4B0_TUNING_SM_CTRL7_ADDR  0x00008237

#define DSC4B0_TUNING_SM_CTRL8_NAME "DSC4B0_TUNING_SM_CTRL8"
#define DSC4B0_TUNING_SM_CTRL8_ADDR  0x00008238

#define DSC4B0_TUNING_SM_CTRL9_NAME "DSC4B0_TUNING_SM_CTRL9"
#define DSC4B0_TUNING_SM_CTRL9_ADDR  0x00008239

#define DSC4B0_TUNING_SM_CTRL10_NAME "DSC4B0_TUNING_SM_CTRL10"
#define DSC4B0_TUNING_SM_CTRL10_ADDR  0x0000823a

#define DSC4B0_TUNING_SM_CTRL11_NAME "DSC4B0_TUNING_SM_CTRL11"
#define DSC4B0_TUNING_SM_CTRL11_ADDR  0x0000823b

#define DSC4B0_ACQ_SM_CTRL9_NAME "DSC4B0_ACQ_SM_CTRL9"
#define DSC4B0_ACQ_SM_CTRL9_ADDR  0x0000823c

#define DSC4B0_ACQ_SM_CTRL10_NAME "DSC4B0_ACQ_SM_CTRL10"
#define DSC4B0_ACQ_SM_CTRL10_ADDR  0x0000823d

#define DSC4B0_ACQ_SM_CTRL11_NAME "DSC4B0_ACQ_SM_CTRL11"
#define DSC4B0_ACQ_SM_CTRL11_ADDR  0x0000823e

#define DSC5B0_TUNING_SM_STATUS0_NAME "DSC5B0_TUNING_SM_STATUS0"
#define DSC5B0_TUNING_SM_STATUS0_ADDR  0x00008240

#define DSC5B0_TUNING_SM_STATUS1_NAME "DSC5B0_TUNING_SM_STATUS1"
#define DSC5B0_TUNING_SM_STATUS1_ADDR  0x00008241

#define DSC5B0_TUNING_SM_STATUS2_NAME "DSC5B0_TUNING_SM_STATUS2"
#define DSC5B0_TUNING_SM_STATUS2_ADDR  0x00008242

#define DSC5B0_TUNING_SM_STATUS3_NAME "DSC5B0_TUNING_SM_STATUS3"
#define DSC5B0_TUNING_SM_STATUS3_ADDR  0x00008243

#define DSC5B0_TUNING_SM_STATUS4_NAME "DSC5B0_TUNING_SM_STATUS4"
#define DSC5B0_TUNING_SM_STATUS4_ADDR  0x00008244

#define DSC5B0_TUNING_SM_STATUS5_NAME "DSC5B0_TUNING_SM_STATUS5"
#define DSC5B0_TUNING_SM_STATUS5_ADDR  0x00008245

#define DSC5B0_TUNING_SM_STATUS6_NAME "DSC5B0_TUNING_SM_STATUS6"
#define DSC5B0_TUNING_SM_STATUS6_ADDR  0x00008246

#define CL72_USER_B0_CL72_XMT_CONTROL_REGISTER_NAME "CL72_USER_B0_CL72_XMT_CONTROL_REGISTER"
#define CL72_USER_B0_CL72_XMT_CONTROL_REGISTER_ADDR  0x000082e0

#define CL72_USER_B0_CL72_RCVD_STATUS_REGISTER_NAME "CL72_USER_B0_CL72_RCVD_STATUS_REGISTER"
#define CL72_USER_B0_CL72_RCVD_STATUS_REGISTER_ADDR  0x000082e1

#define CL72_USER_B0_CL72_TX_FIR_TAP_REGISTER_NAME "CL72_USER_B0_CL72_TX_FIR_TAP_REGISTER"
#define CL72_USER_B0_CL72_TX_FIR_TAP_REGISTER_ADDR  0x000082e2

#define CL72_USER_B0_CL72_MISC1_CONTROL_NAME "CL72_USER_B0_CL72_MISC1_CONTROL"
#define CL72_USER_B0_CL72_MISC1_CONTROL_ADDR  0x000082e3

#define CL72_USER_B0_CL72_MISC2_CONTROL_NAME "CL72_USER_B0_CL72_MISC2_CONTROL"
#define CL72_USER_B0_CL72_MISC2_CONTROL_ADDR  0x000082e4

#define CL72_USER_B0_CL72_KR_DEFAULT_CONTROL_NAME "CL72_USER_B0_CL72_KR_DEFAULT_CONTROL"
#define CL72_USER_B0_CL72_KR_DEFAULT_CONTROL_ADDR  0x000082e5

#define CL72_USER_B0_CL72_OS_DEFAULT_CONTROL_NAME "CL72_USER_B0_CL72_OS_DEFAULT_CONTROL"
#define CL72_USER_B0_CL72_OS_DEFAULT_CONTROL_ADDR  0x000082e6

#define CL72_USER_B0_CL72_BR_DEFAULT_CONTROL_NAME "CL72_USER_B0_CL72_BR_DEFAULT_CONTROL"
#define CL72_USER_B0_CL72_BR_DEFAULT_CONTROL_ADDR  0x000082e7

#define CL72_USER_B0_CL72_2P5_DEFAULT_CONTROL_NAME "CL72_USER_B0_CL72_2P5_DEFAULT_CONTROL"
#define CL72_USER_B0_CL72_2P5_DEFAULT_CONTROL_ADDR  0x000082e8

#define CL72_USER_B0_CL72_TAP_LIMIT_CONTROL_NAME "CL72_USER_B0_CL72_TAP_LIMIT_CONTROL"
#define CL72_USER_B0_CL72_TAP_LIMIT_CONTROL_ADDR  0x000082e9

#define CL72_USER_B0_CL72_MISC3_CONTROL_NAME "CL72_USER_B0_CL72_MISC3_CONTROL"
#define CL72_USER_B0_CL72_MISC3_CONTROL_ADDR  0x000082ea

#define CL72_USER_B0_CL72_TAP_PRESET_CONTROL_NAME "CL72_USER_B0_CL72_TAP_PRESET_CONTROL"
#define CL72_USER_B0_CL72_TAP_PRESET_CONTROL_ADDR  0x000082eb

#define CL72_USER_B0_CL72_MISC4_CONTROL_NAME "CL72_USER_B0_CL72_MISC4_CONTROL"
#define CL72_USER_B0_CL72_MISC4_CONTROL_ADDR  0x000082ec

#define CL72_USER_B1_CL72_FAULT_REGISTER_NAME "CL72_USER_B1_CL72_FAULT_REGISTER"
#define CL72_USER_B1_CL72_FAULT_REGISTER_ADDR  0x000082f9

#define CL72_USER_B1_CL72_DEBUG_1_REGISTER_NAME "CL72_USER_B1_CL72_DEBUG_1_REGISTER"
#define CL72_USER_B1_CL72_DEBUG_1_REGISTER_ADDR  0x000082fb

#define CL72_USER_B1_CL72_DEBUG_2_REGISTER_NAME "CL72_USER_B1_CL72_DEBUG_2_REGISTER"
#define CL72_USER_B1_CL72_DEBUG_2_REGISTER_ADDR  0x000082fc

#define CL72_USER_B1_CL72_DEBUG_3_REGISTER_NAME "CL72_USER_B1_CL72_DEBUG_3_REGISTER"
#define CL72_USER_B1_CL72_DEBUG_3_REGISTER_ADDR  0x000082fd

#define CL72_USER_B1_CL72_DEBUG_4_REGISTER_NAME "CL72_USER_B1_CL72_DEBUG_4_REGISTER"
#define CL72_USER_B1_CL72_DEBUG_4_REGISTER_ADDR  0x000082fe

#define SERDESDIGITAL_CONTROL1000X1_NAME "SERDESDIGITAL_CONTROL1000X1"
#define SERDESDIGITAL_CONTROL1000X1_ADDR  0x00008300

#define SERDESDIGITAL_CONTROL1000X2_NAME "SERDESDIGITAL_CONTROL1000X2"
#define SERDESDIGITAL_CONTROL1000X2_ADDR  0x00008301

#define SERDESDIGITAL_CONTROL1000X3_NAME "SERDESDIGITAL_CONTROL1000X3"
#define SERDESDIGITAL_CONTROL1000X3_ADDR  0x00008302

#define SERDESDIGITAL_CONTROL1000X4_NAME "SERDESDIGITAL_CONTROL1000X4"
#define SERDESDIGITAL_CONTROL1000X4_ADDR  0x00008303

#define SERDESDIGITAL_STATUS1000X1_NAME "SERDESDIGITAL_STATUS1000X1"
#define SERDESDIGITAL_STATUS1000X1_ADDR  0x00008304

#define SERDESDIGITAL_STATUS1000X2_NAME "SERDESDIGITAL_STATUS1000X2"
#define SERDESDIGITAL_STATUS1000X2_ADDR  0x00008305

#define SERDESDIGITAL_STATUS1000X3_NAME "SERDESDIGITAL_STATUS1000X3"
#define SERDESDIGITAL_STATUS1000X3_ADDR  0x00008306

#define SERDESDIGITAL_BADCODEGROUP_NAME "SERDESDIGITAL_BADCODEGROUP"
#define SERDESDIGITAL_BADCODEGROUP_ADDR  0x00008307

#define SERDESDIGITAL_MISC1_NAME "SERDESDIGITAL_MISC1"
#define SERDESDIGITAL_MISC1_ADDR  0x00008308

#define SERDESDIGITAL_MISC2_NAME "SERDESDIGITAL_MISC2"
#define SERDESDIGITAL_MISC2_ADDR  0x00008309

#define SERDESDIGITAL_PATGENCTRL_NAME "SERDESDIGITAL_PATGENCTRL"
#define SERDESDIGITAL_PATGENCTRL_ADDR  0x0000830a

#define SERDESDIGITAL_PATGENSTAT_NAME "SERDESDIGITAL_PATGENSTAT"
#define SERDESDIGITAL_PATGENSTAT_ADDR  0x0000830b

#define SERDESDIGITAL_TESTMODE_NAME "SERDESDIGITAL_TESTMODE"
#define SERDESDIGITAL_TESTMODE_ADDR  0x0000830c

#define SERDESDIGITAL_TXPKTCNT_NAME "SERDESDIGITAL_TXPKTCNT"
#define SERDESDIGITAL_TXPKTCNT_ADDR  0x0000830d

#define SERDESDIGITAL_RXPKTCNT_NAME "SERDESDIGITAL_RXPKTCNT"
#define SERDESDIGITAL_RXPKTCNT_ADDR  0x0000830e

#define SERDESID_SERDESID0_NAME "SERDESID_SERDESID0"
#define SERDESID_SERDESID0_ADDR  0x00008310

#define SERDESID_SERDESID1_NAME "SERDESID_SERDESID1"
#define SERDESID_SERDESID1_ADDR  0x00008311

#define SERDESID_SERDESID2_NAME "SERDESID_SERDESID2"
#define SERDESID_SERDESID2_ADDR  0x00008312

#define SERDESID_SERDESID3_NAME "SERDESID_SERDESID3"
#define SERDESID_SERDESID3_ADDR  0x00008313

#define DIGITAL3_DIGCTL_3_0_NAME "DIGITAL3_DIGCTL_3_0"
#define DIGITAL3_DIGCTL_3_0_ADDR  0x00008320

#define DIGITAL3_DIGCTL_3_1_NAME "DIGITAL3_DIGCTL_3_1"
#define DIGITAL3_DIGCTL_3_1_ADDR  0x00008321

#define DIGITAL3_DIGCTL_3_2_NAME "DIGITAL3_DIGCTL_3_2"
#define DIGITAL3_DIGCTL_3_2_ADDR  0x00008322

#define DIGITAL3_DIGCTL_3_3_NAME "DIGITAL3_DIGCTL_3_3"
#define DIGITAL3_DIGCTL_3_3_ADDR  0x00008323

#define DIGITAL3_DIGCTL_3_4_NAME "DIGITAL3_DIGCTL_3_4"
#define DIGITAL3_DIGCTL_3_4_ADDR  0x00008324

#define DIGITAL3_DIGCTL_3_5_NAME "DIGITAL3_DIGCTL_3_5"
#define DIGITAL3_DIGCTL_3_5_ADDR  0x00008325

#define DIGITAL3_DIGCTL_3_6_NAME "DIGITAL3_DIGCTL_3_6"
#define DIGITAL3_DIGCTL_3_6_ADDR  0x00008326

#define DIGITAL3_TPOUT_1_NAME "DIGITAL3_TPOUT_1"
#define DIGITAL3_TPOUT_1_ADDR  0x00008327

#define DIGITAL3_TPOUT_2_NAME "DIGITAL3_TPOUT_2"
#define DIGITAL3_TPOUT_2_ADDR  0x00008328

#define DIGITAL3_UP1_NAME "DIGITAL3_UP1"
#define DIGITAL3_UP1_ADDR  0x00008329

#define DIGITAL3_UP2_NAME "DIGITAL3_UP2"
#define DIGITAL3_UP2_ADDR  0x0000832a

#define DIGITAL3_UP3_NAME "DIGITAL3_UP3"
#define DIGITAL3_UP3_ADDR  0x0000832b

#define DIGITAL3_LP_UP1_NAME "DIGITAL3_LP_UP1"
#define DIGITAL3_LP_UP1_ADDR  0x0000832c

#define DIGITAL3_LP_UP2_NAME "DIGITAL3_LP_UP2"
#define DIGITAL3_LP_UP2_ADDR  0x0000832d

#define DIGITAL3_LP_UP3_NAME "DIGITAL3_LP_UP3"
#define DIGITAL3_LP_UP3_ADDR  0x0000832e

#define DIGITAL4_MISCRXSTATUS_NAME "DIGITAL4_MISCRXSTATUS"
#define DIGITAL4_MISCRXSTATUS_ADDR  0x00008330

#define DIGITAL4_LP_BASEPAGE_NAME "DIGITAL4_LP_BASEPAGE"
#define DIGITAL4_LP_BASEPAGE_ADDR  0x00008331

#define DIGITAL4_LP_NEXTPAGE_0_NAME "DIGITAL4_LP_NEXTPAGE_0"
#define DIGITAL4_LP_NEXTPAGE_0_ADDR  0x00008332

#define DIGITAL4_LP_NEXTPAGE_1_NAME "DIGITAL4_LP_NEXTPAGE_1"
#define DIGITAL4_LP_NEXTPAGE_1_ADDR  0x00008333

#define DIGITAL4_LP_NEXTPAGE_2_NAME "DIGITAL4_LP_NEXTPAGE_2"
#define DIGITAL4_LP_NEXTPAGE_2_ADDR  0x00008334

#define DIGITAL4_LP_NEXTPAGE_3_NAME "DIGITAL4_LP_NEXTPAGE_3"
#define DIGITAL4_LP_NEXTPAGE_3_ADDR  0x00008335

#define DIGITAL4_LP_NEXTPAGE_4_NAME "DIGITAL4_LP_NEXTPAGE_4"
#define DIGITAL4_LP_NEXTPAGE_4_ADDR  0x00008336

#define DIGITAL4_RP_NEXTPAGE_0_NAME "DIGITAL4_RP_NEXTPAGE_0"
#define DIGITAL4_RP_NEXTPAGE_0_ADDR  0x00008337

#define DIGITAL4_RP_NEXTPAGE_1_NAME "DIGITAL4_RP_NEXTPAGE_1"
#define DIGITAL4_RP_NEXTPAGE_1_ADDR  0x00008338

#define DIGITAL4_RP_NEXTPAGE_2_NAME "DIGITAL4_RP_NEXTPAGE_2"
#define DIGITAL4_RP_NEXTPAGE_2_ADDR  0x00008339

#define DIGITAL4_RP_NEXTPAGE_3_NAME "DIGITAL4_RP_NEXTPAGE_3"
#define DIGITAL4_RP_NEXTPAGE_3_ADDR  0x0000833a

#define DIGITAL4_RP_NEXTPAGE_4_NAME "DIGITAL4_RP_NEXTPAGE_4"
#define DIGITAL4_RP_NEXTPAGE_4_ADDR  0x0000833b

#define DIGITAL4_MISC3_NAME "DIGITAL4_MISC3"
#define DIGITAL4_MISC3_ADDR  0x0000833c

#define DIGITAL4_MISC4_NAME "DIGITAL4_MISC4"
#define DIGITAL4_MISC4_ADDR  0x0000833d

#define DIGITAL4_MISC5_NAME "DIGITAL4_MISC5"
#define DIGITAL4_MISC5_ADDR  0x0000833e

#define DIGITAL5_LINKCNT_CL72_LSB_NAME "DIGITAL5_LINKCNT_CL72_LSB"
#define DIGITAL5_LINKCNT_CL72_LSB_ADDR  0x00008340

#define DIGITAL5_LINKCNT_CL72_MSB_NAME "DIGITAL5_LINKCNT_CL72_MSB"
#define DIGITAL5_LINKCNT_CL72_MSB_ADDR  0x00008341

#define DIGITAL5_LP_UP4_NAME "DIGITAL5_LP_UP4"
#define DIGITAL5_LP_UP4_ADDR  0x00008342

#define DIGITAL5_LP_UP5_NAME "DIGITAL5_LP_UP5"
#define DIGITAL5_LP_UP5_ADDR  0x00008343

#define DIGITAL5_LPI_HYST_NAME "DIGITAL5_LPI_HYST"
#define DIGITAL5_LPI_HYST_ADDR  0x00008344

#define DIGITAL5_MISC6_NAME "DIGITAL5_MISC6"
#define DIGITAL5_MISC6_ADDR  0x00008345

#define DIGITAL5_ACTUAL_SPEED_NAME "DIGITAL5_ACTUAL_SPEED"
#define DIGITAL5_ACTUAL_SPEED_ADDR  0x0000834e

#define DIGITAL6_MP5_NEXTPAGECTRL_NAME "DIGITAL6_MP5_NEXTPAGECTRL"
#define DIGITAL6_MP5_NEXTPAGECTRL_ADDR  0x00008350

#define DIGITAL6_LINK_TIMER_OFFSET1_NAME "DIGITAL6_LINK_TIMER_OFFSET1"
#define DIGITAL6_LINK_TIMER_OFFSET1_ADDR  0x00008351

#define DIGITAL6_LINK_TIMER_OFFSET2_NAME "DIGITAL6_LINK_TIMER_OFFSET2"
#define DIGITAL6_LINK_TIMER_OFFSET2_ADDR  0x00008352

#define DIGITAL6_LINK_TIMER_OFFSET3_NAME "DIGITAL6_LINK_TIMER_OFFSET3"
#define DIGITAL6_LINK_TIMER_OFFSET3_ADDR  0x00008353

#define DIGITAL6_OUI_MSB_FIELD_NAME "DIGITAL6_OUI_MSB_FIELD"
#define DIGITAL6_OUI_MSB_FIELD_ADDR  0x00008354

#define DIGITAL6_OUI_LSB_FIELD_NAME "DIGITAL6_OUI_LSB_FIELD"
#define DIGITAL6_OUI_LSB_FIELD_ADDR  0x00008355

#define DIGITAL6_BAM_FIELD_NAME "DIGITAL6_BAM_FIELD"
#define DIGITAL6_BAM_FIELD_ADDR  0x00008356

#define DIGITAL6_UD_FIELD_NAME "DIGITAL6_UD_FIELD"
#define DIGITAL6_UD_FIELD_ADDR  0x00008357

#define DIGITAL6_LP_OUI_MSB_FIELD_NAME "DIGITAL6_LP_OUI_MSB_FIELD"
#define DIGITAL6_LP_OUI_MSB_FIELD_ADDR  0x00008358

#define DIGITAL6_LP_OUI_LSB_FIELD_NAME "DIGITAL6_LP_OUI_LSB_FIELD"
#define DIGITAL6_LP_OUI_LSB_FIELD_ADDR  0x00008359

#define DIGITAL6_LP_BAM_FIELD_NAME "DIGITAL6_LP_BAM_FIELD"
#define DIGITAL6_LP_BAM_FIELD_ADDR  0x0000835a

#define DIGITAL6_LP_UD_FIELD_NAME "DIGITAL6_LP_UD_FIELD"
#define DIGITAL6_LP_UD_FIELD_ADDR  0x0000835b

#define DIGITAL6_UP4_NAME "DIGITAL6_UP4"
#define DIGITAL6_UP4_ADDR  0x0000835d

#define DIGITAL6_UP5_NAME "DIGITAL6_UP5"
#define DIGITAL6_UP5_ADDR  0x0000835e

#define CL49_USERB0_CONTROL1_NAME "CL49_USERB0_CONTROL1"
#define CL49_USERB0_CONTROL1_ADDR  0x00008360

#define CL49_USERB0_STATUS1_NAME "CL49_USERB0_STATUS1"
#define CL49_USERB0_STATUS1_ADDR  0x00008361

#define CL49_USERB0_SYMBOLDETECT_NAME "CL49_USERB0_SYMBOLDETECT"
#define CL49_USERB0_SYMBOLDETECT_ADDR  0x00008362

#define CL49_USERB0_SYMBOLINSERT_NAME "CL49_USERB0_SYMBOLINSERT"
#define CL49_USERB0_SYMBOLINSERT_ADDR  0x00008363

#define CL49_USERB0_CONTROL2_NAME "CL49_USERB0_CONTROL2"
#define CL49_USERB0_CONTROL2_ADDR  0x00008364

#define CL49_USERB0_TXSM_STATUS_NAME "CL49_USERB0_TXSM_STATUS"
#define CL49_USERB0_TXSM_STATUS_ADDR  0x00008365

#define CL49_USERB0_RXSM_STATUS_NAME "CL49_USERB0_RXSM_STATUS"
#define CL49_USERB0_RXSM_STATUS_ADDR  0x00008366

#define CL49_USERB0_LSM_STATUS_NAME "CL49_USERB0_LSM_STATUS"
#define CL49_USERB0_LSM_STATUS_ADDR  0x00008367

#define CL49_USERB0_CONTROL_NAME "CL49_USERB0_CONTROL"
#define CL49_USERB0_CONTROL_ADDR  0x00008368

#define CL49_USERB0_STATUS_NAME "CL49_USERB0_STATUS"
#define CL49_USERB0_STATUS_ADDR  0x00008369

#define CL49_USERB0_SHCOUNTER_NAME "CL49_USERB0_SHCOUNTER"
#define CL49_USERB0_SHCOUNTER_ADDR  0x0000836a

#define CL49_USERB0_TIMER125US_NAME "CL49_USERB0_TIMER125US"
#define CL49_USERB0_TIMER125US_ADDR  0x0000836b

#define CL49_USERB0_BERCNT_NAME "CL49_USERB0_BERCNT"
#define CL49_USERB0_BERCNT_ADDR  0x0000836c

#define CL49_USERB0_BERMON_STATUS_NAME "CL49_USERB0_BERMON_STATUS"
#define CL49_USERB0_BERMON_STATUS_ADDR  0x0000836d

#define CL49_USERB0_TSTCNT1_NAME "CL49_USERB0_TSTCNT1"
#define CL49_USERB0_TSTCNT1_ADDR  0x0000836e

#define CL73_USERB0_CL73_UCTRL1_NAME "CL73_USERB0_CL73_UCTRL1"
#define CL73_USERB0_CL73_UCTRL1_ADDR  0x00008370

#define CL73_USERB0_CL73_USTAT1_NAME "CL73_USERB0_CL73_USTAT1"
#define CL73_USERB0_CL73_USTAT1_ADDR  0x00008371

#define CL73_USERB0_CL73_BAMCTRL1_NAME "CL73_USERB0_CL73_BAMCTRL1"
#define CL73_USERB0_CL73_BAMCTRL1_ADDR  0x00008372

#define CL73_USERB0_CL73_BAMCTRL2_NAME "CL73_USERB0_CL73_BAMCTRL2"
#define CL73_USERB0_CL73_BAMCTRL2_ADDR  0x00008373

#define CL73_USERB0_CL73_BAMCTRL3_NAME "CL73_USERB0_CL73_BAMCTRL3"
#define CL73_USERB0_CL73_BAMCTRL3_ADDR  0x00008374

#define CL73_USERB0_CL73_BAMSTAT1_NAME "CL73_USERB0_CL73_BAMSTAT1"
#define CL73_USERB0_CL73_BAMSTAT1_ADDR  0x00008375

#define CL73_USERB0_CL73_BAMSTAT2_NAME "CL73_USERB0_CL73_BAMSTAT2"
#define CL73_USERB0_CL73_BAMSTAT2_ADDR  0x00008376

#define CL73_USERB0_CL73_BAMSTAT3_NAME "CL73_USERB0_CL73_BAMSTAT3"
#define CL73_USERB0_CL73_BAMSTAT3_ADDR  0x00008377

#define CL73_USERB0_CL73_UCTRL2_NAME "CL73_USERB0_CL73_UCTRL2"
#define CL73_USERB0_CL73_UCTRL2_ADDR  0x00008378

#define CL73_USERB0_CL73_UCTRL3_NAME "CL73_USERB0_CL73_UCTRL3"
#define CL73_USERB0_CL73_UCTRL3_ADDR  0x00008379

#define CL73_USERB0_CL73_UCTRL4_NAME "CL73_USERB0_CL73_UCTRL4"
#define CL73_USERB0_CL73_UCTRL4_ADDR  0x0000837a

#define CL73_USERB0_CL73_EEECTRL_NAME "CL73_USERB0_CL73_EEECTRL"
#define CL73_USERB0_CL73_EEECTRL_ADDR  0x0000837e

#define CL74_USERB0_UFECCONTROL1_NAME "CL74_USERB0_UFECCONTROL1"
#define CL74_USERB0_UFECCONTROL1_ADDR  0x00008380

#define CL74_USERB0_UFECCONTROL2_NAME "CL74_USERB0_UFECCONTROL2"
#define CL74_USERB0_UFECCONTROL2_ADDR  0x00008381

#define CL74_USERB0_UFECCONTROL3_NAME "CL74_USERB0_UFECCONTROL3"
#define CL74_USERB0_UFECCONTROL3_ADDR  0x00008382

#define CL74_USERB0_UFECDBG_EDATAL_NAME "CL74_USERB0_UFECDBG_EDATAL"
#define CL74_USERB0_UFECDBG_EDATAL_ADDR  0x00008383

#define CL74_USERB0_UFECDBG_EDATAH_NAME "CL74_USERB0_UFECDBG_EDATAH"
#define CL74_USERB0_UFECDBG_EDATAH_ADDR  0x00008384

#define EEE_USERB0_EEE_COMBO_CONTROL0_NAME "EEE_USERB0_EEE_COMBO_CONTROL0"
#define EEE_USERB0_EEE_COMBO_CONTROL0_ADDR  0x00008390

#define EEE_USERB0_CL36_TX_LPI_SM_NAME "EEE_USERB0_CL36_TX_LPI_SM"
#define EEE_USERB0_CL36_TX_LPI_SM_ADDR  0x00008391

#define EEE_USERB0_CL36_RX_LPI_SM_NAME "EEE_USERB0_CL36_RX_LPI_SM"
#define EEE_USERB0_CL36_RX_LPI_SM_ADDR  0x00008392

#define EEE_USERB0_CL49_TX_LPI_SM_NAME "EEE_USERB0_CL49_TX_LPI_SM"
#define EEE_USERB0_CL49_TX_LPI_SM_ADDR  0x00008393

#define EEE_USERB0_CL49_RX_LPI_SM_NAME "EEE_USERB0_CL49_RX_LPI_SM"
#define EEE_USERB0_CL49_RX_LPI_SM_ADDR  0x00008394

#define EEE_USERB0_TX_SLEEP_TIMER_NAME "EEE_USERB0_TX_SLEEP_TIMER"
#define EEE_USERB0_TX_SLEEP_TIMER_ADDR  0x00008395

#define EEE_USERB0_CL49_TX_SLEEP_TIMER_NAME "EEE_USERB0_CL49_TX_SLEEP_TIMER"
#define EEE_USERB0_CL49_TX_SLEEP_TIMER_ADDR  0x00008396

#define EEE_USERB0_TX_WAKE_TIMER_NAME "EEE_USERB0_TX_WAKE_TIMER"
#define EEE_USERB0_TX_WAKE_TIMER_ADDR  0x00008397

#define EEE_USERB0_RX_OFFSET_TIMER_NAME "EEE_USERB0_RX_OFFSET_TIMER"
#define EEE_USERB0_RX_OFFSET_TIMER_ADDR  0x00008398

#define EEE_USERB0_RX_WAKE_TIME_FAULT_TIMER_NAME "EEE_USERB0_RX_WAKE_TIME_FAULT_TIMER"
#define EEE_USERB0_RX_WAKE_TIME_FAULT_TIMER_ADDR  0x00008399

#define EEE_USERB0_MISC_TIMER_NAME "EEE_USERB0_MISC_TIMER"
#define EEE_USERB0_MISC_TIMER_ADDR  0x0000839a

#define EEE_USERB0_EEE_HYST_TIMER_NAME "EEE_USERB0_EEE_HYST_TIMER"
#define EEE_USERB0_EEE_HYST_TIMER_ADDR  0x0000839b

#define EEE_USERB0_EEE_OVERRIDE_CTRL_NAME "EEE_USERB0_EEE_OVERRIDE_CTRL"
#define EEE_USERB0_EEE_OVERRIDE_CTRL_ADDR  0x0000839c

#define EEE_USERB0_EEE_COMBO_CONTROL1_NAME "EEE_USERB0_EEE_COMBO_CONTROL1"
#define EEE_USERB0_EEE_COMBO_CONTROL1_ADDR  0x0000839d

#define EEE_USERB0_CL49_EEE_CHAR_NAME "EEE_USERB0_CL49_EEE_CHAR"
#define EEE_USERB0_CL49_EEE_CHAR_ADDR  0x0000839e

#define EEE_USERB1_EEE_AN_CTRL_NAME "EEE_USERB1_EEE_AN_CTRL"
#define EEE_USERB1_EEE_AN_CTRL_ADDR  0x000083a0

#define EEE_USERB1_EEE_UP1_NAME "EEE_USERB1_EEE_UP1"
#define EEE_USERB1_EEE_UP1_ADDR  0x000083a1

#define EEE_USERB1_EEE_UP2_NAME "EEE_USERB1_EEE_UP2"
#define EEE_USERB1_EEE_UP2_ADDR  0x000083a2

#define EEE_USERB1_EEE_UP3_NAME "EEE_USERB1_EEE_UP3"
#define EEE_USERB1_EEE_UP3_ADDR  0x000083a3

#define EEE_USERB1_LP_EEE_UP1_NAME "EEE_USERB1_LP_EEE_UP1"
#define EEE_USERB1_LP_EEE_UP1_ADDR  0x000083a4

#define EEE_USERB1_LP_EEE_UP2_NAME "EEE_USERB1_LP_EEE_UP2"
#define EEE_USERB1_LP_EEE_UP2_ADDR  0x000083a5

#define EEE_USERB1_LP_EEE_UP3_NAME "EEE_USERB1_LP_EEE_UP3"
#define EEE_USERB1_LP_EEE_UP3_ADDR  0x000083a6

#define EEE_USERB1_EEE_RES_STATUS_NAME "EEE_USERB1_EEE_RES_STATUS"
#define EEE_USERB1_EEE_RES_STATUS_ADDR  0x000083a7

#define TX66_CONTROL_NAME "TX66_CONTROL"
#define TX66_CONTROL_ADDR  0x000083b0

#define TX66_STATUS_NAME "TX66_STATUS"
#define TX66_STATUS_ADDR  0x000083b1

#define TX66_PROGMMABLE_TL_NAME "TX66_PROGMMABLE_TL"
#define TX66_PROGMMABLE_TL_ADDR  0x000083b2

#define RX66_CONTROL_NAME "RX66_CONTROL"
#define RX66_CONTROL_ADDR  0x000083c0

#define RX66_STATUS_NAME "RX66_STATUS"
#define RX66_STATUS_ADDR  0x000083c1

#define RX66_SCW0_NAME "RX66_SCW0"
#define RX66_SCW0_ADDR  0x000083c2

#define RX66_SCW1_NAME "RX66_SCW1"
#define RX66_SCW1_ADDR  0x000083c3

#define RX66_SCW2_NAME "RX66_SCW2"
#define RX66_SCW2_ADDR  0x000083c4

#define RX66_SCW3_NAME "RX66_SCW3"
#define RX66_SCW3_ADDR  0x000083c5

#define RX66_SCW0_MASK_NAME "RX66_SCW0_MASK"
#define RX66_SCW0_MASK_ADDR  0x000083c6

#define RX66_SCW1_MASK_NAME "RX66_SCW1_MASK"
#define RX66_SCW1_MASK_ADDR  0x000083c7

#define RX66_SCW2_MASK_NAME "RX66_SCW2_MASK"
#define RX66_SCW2_MASK_ADDR  0x000083c8

#define RX66_SCW3_MASK_NAME "RX66_SCW3_MASK"
#define RX66_SCW3_MASK_ADDR  0x000083c9

#define RX66_SYNCBITS_NAME "RX66_SYNCBITS"
#define RX66_SYNCBITS_ADDR  0x000083ca

#define RX66_SCWCONTROL_NAME "RX66_SCWCONTROL"
#define RX66_SCWCONTROL_ADDR  0x000083cb

#define RX66_CC_EVENTCOUNT_NAME "RX66_CC_EVENTCOUNT"
#define RX66_CC_EVENTCOUNT_ADDR  0x000083cc

#define RX66_SCWCOUNT_NAME "RX66_SCWCOUNT"
#define RX66_SCWCOUNT_ADDR  0x000083cd

#define RX66_ERRCOUNT_NAME "RX66_ERRCOUNT"
#define RX66_ERRCOUNT_ADDR  0x000083ce

#define LNTXBERT_TXBERTCTRL_NAME "LNTXBERT_TXBERTCTRL"
#define LNTXBERT_TXBERTCTRL_ADDR  0x000083d0

#define LNTXBERT_TXBERTSOPEOP_NAME "LNTXBERT_TXBERTSOPEOP"
#define LNTXBERT_TXBERTSOPEOP_ADDR  0x000083d1

#define LNTXBERT_TXBERTSIZE0_NAME "LNTXBERT_TXBERTSIZE0"
#define LNTXBERT_TXBERTSIZE0_ADDR  0x000083d2

#define LNTXBERT_TXBERTSIZE1_NAME "LNTXBERT_TXBERTSIZE1"
#define LNTXBERT_TXBERTSIZE1_ADDR  0x000083d3

#define LNTXBERT_TXBERTSIZE2_NAME "LNTXBERT_TXBERTSIZE2"
#define LNTXBERT_TXBERTSIZE2_ADDR  0x000083d4

#define LNTXBERT_TXBERTIPG0_NAME "LNTXBERT_TXBERTIPG0"
#define LNTXBERT_TXBERTIPG0_ADDR  0x000083d5

#define LNTXBERT_TXBERTIPG1_NAME "LNTXBERT_TXBERTIPG1"
#define LNTXBERT_TXBERTIPG1_ADDR  0x000083d6

#define LNTXBERT_TXBERTBYTEU_NAME "LNTXBERT_TXBERTBYTEU"
#define LNTXBERT_TXBERTBYTEU_ADDR  0x000083d7

#define LNTXBERT_TXBERTBYTEL_NAME "LNTXBERT_TXBERTBYTEL"
#define LNTXBERT_TXBERTBYTEL_ADDR  0x000083d8

#define LNTXBERT_TXBERTPACKETU_NAME "LNTXBERT_TXBERTPACKETU"
#define LNTXBERT_TXBERTPACKETU_ADDR  0x000083d9

#define LNTXBERT_TXBERTPACKETL_NAME "LNTXBERT_TXBERTPACKETL"
#define LNTXBERT_TXBERTPACKETL_ADDR  0x000083da

#define LNTXBERT_TXBERTCTRL1_NAME "LNTXBERT_TXBERTCTRL1"
#define LNTXBERT_TXBERTCTRL1_ADDR  0x000083db

#define LNRXBERT_RXBERTCTRL_NAME "LNRXBERT_RXBERTCTRL"
#define LNRXBERT_RXBERTCTRL_ADDR  0x000083e0

#define LNRXBERT_RXBERTSOPEOP_NAME "LNRXBERT_RXBERTSOPEOP"
#define LNRXBERT_RXBERTSOPEOP_ADDR  0x000083e1

#define LNRXBERT_RXBERTBYTEU_NAME "LNRXBERT_RXBERTBYTEU"
#define LNRXBERT_RXBERTBYTEU_ADDR  0x000083e7

#define LNRXBERT_RXBERTBYTEL_NAME "LNRXBERT_RXBERTBYTEL"
#define LNRXBERT_RXBERTBYTEL_ADDR  0x000083e8

#define LNRXBERT_RXBERTPACKETU_NAME "LNRXBERT_RXBERTPACKETU"
#define LNRXBERT_RXBERTPACKETU_ADDR  0x000083e9

#define LNRXBERT_RXBERTPACKETL_NAME "LNRXBERT_RXBERTPACKETL"
#define LNRXBERT_RXBERTPACKETL_ADDR  0x000083ea

#define LNRXBERT_RXBERTBITERR_NAME "LNRXBERT_RXBERTBITERR"
#define LNRXBERT_RXBERTBITERR_ADDR  0x000083eb

#define LNRXBERT_RXBERTBYTEERR_NAME "LNRXBERT_RXBERTBYTEERR"
#define LNRXBERT_RXBERTBYTEERR_ADDR  0x000083ec

#define LNRXBERT_RXBERTPKTERR_NAME "LNRXBERT_RXBERTPKTERR"
#define LNRXBERT_RXBERTPKTERR_ADDR  0x000083ed

#define LNRXBERT_RXBERTSTATUS_NAME "LNRXBERT_RXBERTSTATUS"
#define LNRXBERT_RXBERTSTATUS_ADDR  0x000083ee

#define FX100_CONTROL1_NAME "FX100_CONTROL1"
#define FX100_CONTROL1_ADDR  0x00008400

#define FX100_CONTROL2_NAME "FX100_CONTROL2"
#define FX100_CONTROL2_ADDR  0x00008401

#define FX100_CONTROL3_NAME "FX100_CONTROL3"
#define FX100_CONTROL3_ADDR  0x00008402

#define FX100_STATUS1_NAME "FX100_STATUS1"
#define FX100_STATUS1_ADDR  0x00008403

#define FX100_STATUS3_NAME "FX100_STATUS3"
#define FX100_STATUS3_ADDR  0x00008405

#define FX100_STATUS4_NAME "FX100_STATUS4"
#define FX100_STATUS4_ADDR  0x00008406

#define FX100_FX100IDLE1_NAME "FX100_FX100IDLE1"
#define FX100_FX100IDLE1_ADDR  0x00008407

#define FX100_FX100IDLE2_NAME "FX100_FX100IDLE2"
#define FX100_FX100IDLE2_ADDR  0x00008408

#define FX100_FX100IDLESTATUS_NAME "FX100_FX100IDLESTATUS"
#define FX100_FX100IDLESTATUS_ADDR  0x00008409

#define FX100_FX100IDLETHRES_NAME "FX100_FX100IDLETHRES"
#define FX100_FX100IDLETHRES_ADDR  0x0000840a

#define FX100_FX100LOCKTMR_NAME "FX100_FX100LOCKTMR"
#define FX100_FX100LOCKTMR_ADDR  0x0000840b

#define FX100_FX100LINKTMR_NAME "FX100_FX100LINKTMR"
#define FX100_FX100LINKTMR_ADDR  0x0000840c

#define EEE_TIMERB0_GRP1_TX_REFRESH_TIMER_NAME "EEE_TIMERB0_GRP1_TX_REFRESH_TIMER"
#define EEE_TIMERB0_GRP1_TX_REFRESH_TIMER_ADDR  0x00008410

#define EEE_TIMERB0_GRP1_TX_QUIET_TIMER_NAME "EEE_TIMERB0_GRP1_TX_QUIET_TIMER"
#define EEE_TIMERB0_GRP1_TX_QUIET_TIMER_ADDR  0x00008411

#define EEE_TIMERB0_GRP1_RX_WAKE_TIMER_NAME "EEE_TIMERB0_GRP1_RX_WAKE_TIMER"
#define EEE_TIMERB0_GRP1_RX_WAKE_TIMER_ADDR  0x00008412

#define EEE_TIMERB0_GRP2_TX_REFRESH_TIMER_NAME "EEE_TIMERB0_GRP2_TX_REFRESH_TIMER"
#define EEE_TIMERB0_GRP2_TX_REFRESH_TIMER_ADDR  0x00008413

#define EEE_TIMERB0_GRP2_TX_QUIET_TIMER_NAME "EEE_TIMERB0_GRP2_TX_QUIET_TIMER"
#define EEE_TIMERB0_GRP2_TX_QUIET_TIMER_ADDR  0x00008414

#define EEE_TIMERB0_GRP2_RX_WAKE_TIMER_NAME "EEE_TIMERB0_GRP2_RX_WAKE_TIMER"
#define EEE_TIMERB0_GRP2_RX_WAKE_TIMER_ADDR  0x00008415

#define EEE_TIMERB0_GRP3_TX_REFRESH_TIMER_NAME "EEE_TIMERB0_GRP3_TX_REFRESH_TIMER"
#define EEE_TIMERB0_GRP3_TX_REFRESH_TIMER_ADDR  0x00008416

#define EEE_TIMERB0_GRP3_TX_QUIET_TIMER_NAME "EEE_TIMERB0_GRP3_TX_QUIET_TIMER"
#define EEE_TIMERB0_GRP3_TX_QUIET_TIMER_ADDR  0x00008417

#define EEE_TIMERB0_GRP3_RX_WAKE_TIMER_NAME "EEE_TIMERB0_GRP3_RX_WAKE_TIMER"
#define EEE_TIMERB0_GRP3_RX_WAKE_TIMER_ADDR  0x00008418

#define EEE_TIMERB0_GRP4_TX_REFRESH_TIMER_NAME "EEE_TIMERB0_GRP4_TX_REFRESH_TIMER"
#define EEE_TIMERB0_GRP4_TX_REFRESH_TIMER_ADDR  0x00008419

#define EEE_TIMERB0_GRP4_TX_QUIET_TIMER_NAME "EEE_TIMERB0_GRP4_TX_QUIET_TIMER"
#define EEE_TIMERB0_GRP4_TX_QUIET_TIMER_ADDR  0x0000841a

#define EEE_TIMERB0_GRP4_RX_WAKE_TIMER_NAME "EEE_TIMERB0_GRP4_RX_WAKE_TIMER"
#define EEE_TIMERB0_GRP4_RX_WAKE_TIMER_ADDR  0x0000841b

#define EEE_TIMERB0_GRP5_TX_REFRESH_TIMER_NAME "EEE_TIMERB0_GRP5_TX_REFRESH_TIMER"
#define EEE_TIMERB0_GRP5_TX_REFRESH_TIMER_ADDR  0x0000841c

#define EEE_TIMERB0_GRP5_TX_QUIET_TIMER_NAME "EEE_TIMERB0_GRP5_TX_QUIET_TIMER"
#define EEE_TIMERB0_GRP5_TX_QUIET_TIMER_ADDR  0x0000841d

#define EEE_TIMERB0_GRP5_RX_WAKE_TIMER_NAME "EEE_TIMERB0_GRP5_RX_WAKE_TIMER"
#define EEE_TIMERB0_GRP5_RX_WAKE_TIMER_ADDR  0x0000841e

#define MICROBLK_RAMWORD_NAME "MICROBLK_RAMWORD"
#define MICROBLK_RAMWORD_ADDR  0x0000ffc0

#define MICROBLK_ADDRESS_NAME "MICROBLK_ADDRESS"
#define MICROBLK_ADDRESS_ADDR  0x0000ffc1

#define MICROBLK_COMMAND_NAME "MICROBLK_COMMAND"
#define MICROBLK_COMMAND_ADDR  0x0000ffc2

#define MICROBLK_WRDATA_NAME "MICROBLK_WRDATA"
#define MICROBLK_WRDATA_ADDR  0x0000ffc3

#define MICROBLK_RDDATA_NAME "MICROBLK_RDDATA"
#define MICROBLK_RDDATA_ADDR  0x0000ffc4

#define MICROBLK_DOWNLOAD_STATUS_NAME "MICROBLK_DOWNLOAD_STATUS"
#define MICROBLK_DOWNLOAD_STATUS_ADDR  0x0000ffc5

#define MICROBLK_SFR_STATUS0_NAME "MICROBLK_SFR_STATUS0"
#define MICROBLK_SFR_STATUS0_ADDR  0x0000ffc6

#define MICROBLK_SFR_STATUS1_NAME "MICROBLK_SFR_STATUS1"
#define MICROBLK_SFR_STATUS1_ADDR  0x0000ffc7

#define MICROBLK_MDIO_UC_MAILBOX_NAME "MICROBLK_MDIO_UC_MAILBOX"
#define MICROBLK_MDIO_UC_MAILBOX_ADDR  0x0000ffc8

#define MICROBLK_UC_MDIO_MAILBOX_NAME "MICROBLK_UC_MDIO_MAILBOX"
#define MICROBLK_UC_MDIO_MAILBOX_ADDR  0x0000ffc9

#define MICROBLK_COMMAND2_NAME "MICROBLK_COMMAND2"
#define MICROBLK_COMMAND2_ADDR  0x0000ffca

#define MICROBLK_WDOG_EVNT_CNT_NAME "MICROBLK_WDOG_EVNT_CNT"
#define MICROBLK_WDOG_EVNT_CNT_ADDR  0x0000ffcb

#define MICROBLK_COMMAND3_NAME "MICROBLK_COMMAND3"
#define MICROBLK_COMMAND3_ADDR  0x0000ffcc

#define AERBLK_AER_NAME "AERBLK_AER"
#define AERBLK_AER_ADDR  0x0000ffde

#define COMBO_IEEE0_MIICNTL_NAME "COMBO_IEEE0_MIICNTL"
#define COMBO_IEEE0_MIICNTL_ADDR  0x0000ffe0

#define COMBO_IEEE0_MIISTAT_NAME "COMBO_IEEE0_MIISTAT"
#define COMBO_IEEE0_MIISTAT_ADDR  0x0000ffe1

#define COMBO_IEEE0_ID1_NAME "COMBO_IEEE0_ID1"
#define COMBO_IEEE0_ID1_ADDR  0x0000ffe2

#define COMBO_IEEE0_ID2_NAME "COMBO_IEEE0_ID2"
#define COMBO_IEEE0_ID2_ADDR  0x0000ffe3

#define COMBO_IEEE0_AUTONEGADV_NAME "COMBO_IEEE0_AUTONEGADV"
#define COMBO_IEEE0_AUTONEGADV_ADDR  0x0000ffe4

#define COMBO_IEEE0_AUTONEGLPABIL_NAME "COMBO_IEEE0_AUTONEGLPABIL"
#define COMBO_IEEE0_AUTONEGLPABIL_ADDR  0x0000ffe5

#define COMBO_IEEE0_AUTONEGEXP_NAME "COMBO_IEEE0_AUTONEGEXP"
#define COMBO_IEEE0_AUTONEGEXP_ADDR  0x0000ffe6

#define COMBO_IEEE0_AUTONEGNP_NAME "COMBO_IEEE0_AUTONEGNP"
#define COMBO_IEEE0_AUTONEGNP_ADDR  0x0000ffe7

#define COMBO_IEEE0_AUTONEGLPABIL2_NAME "COMBO_IEEE0_AUTONEGLPABIL2"
#define COMBO_IEEE0_AUTONEGLPABIL2_ADDR  0x0000ffe8

#define COMBO_IEEE0_MIIEXTSTAT_NAME "COMBO_IEEE0_MIIEXTSTAT"
#define COMBO_IEEE0_MIIEXTSTAT_ADDR  0x0000ffef

#define PMD_IEEE0BLK_PMD_IEEECONTROL1_NAME "PMD_IEEE0BLK_PMD_IEEECONTROL1"
#define PMD_IEEE0BLK_PMD_IEEECONTROL1_ADDR  0x08000000

#define PMD_IEEE0BLK_PMD_IEEESTATUS1_NAME "PMD_IEEE0BLK_PMD_IEEESTATUS1"
#define PMD_IEEE0BLK_PMD_IEEESTATUS1_ADDR  0x08000001

#define PMD_IEEE0BLK_PMD_IEEEID1_NAME "PMD_IEEE0BLK_PMD_IEEEID1"
#define PMD_IEEE0BLK_PMD_IEEEID1_ADDR  0x08000002

#define PMD_IEEE0BLK_PMD_IEEEID2_NAME "PMD_IEEE0BLK_PMD_IEEEID2"
#define PMD_IEEE0BLK_PMD_IEEEID2_ADDR  0x08000003

#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_NAME "PMD_IEEE0BLK_PMD_IEEESPEEDABILITY"
#define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_ADDR  0x08000004

#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_NAME "PMD_IEEE0BLK_PMD_IEEEDEVINPKG1"
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_ADDR  0x08000005

#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_NAME "PMD_IEEE0BLK_PMD_IEEEDEVINPKG2"
#define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_ADDR  0x08000006

#define PMD_IEEE0BLK_PMD_IEEECONTROL2_NAME "PMD_IEEE0BLK_PMD_IEEECONTROL2"
#define PMD_IEEE0BLK_PMD_IEEECONTROL2_ADDR  0x08000007

#define PMD_IEEE0BLK_PMD_IEEESTATUS2_NAME "PMD_IEEE0BLK_PMD_IEEESTATUS2"
#define PMD_IEEE0BLK_PMD_IEEESTATUS2_ADDR  0x08000008

#define PMD_IEEE0BLK_PMD_TXDISABLE_NAME "PMD_IEEE0BLK_PMD_TXDISABLE"
#define PMD_IEEE0BLK_PMD_TXDISABLE_ADDR  0x08000009

#define PMD_IEEE0BLK_PMD_RXSIGDET_NAME "PMD_IEEE0BLK_PMD_RXSIGDET"
#define PMD_IEEE0BLK_PMD_RXSIGDET_ADDR  0x0800000a

#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_NAME "PMD_IEEE0BLK_PMD_EXTENDEDABILITY"
#define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_ADDR  0x0800000b

#define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_NAME "PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150"
#define PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150_ADDR  0x08000096

#define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_NAME "PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151"
#define PMD_IEEE9BLK_TENGBASE_KR_PMD_STATUS_REGISTER_151_ADDR  0x08000097

#define PMD_IEEE9BLK_TENGBASE_KR_LP_COEFFICIENT_UPD_152_NAME "PMD_IEEE9BLK_TENGBASE_KR_LP_COEFFICIENT_UPD_152"
#define PMD_IEEE9BLK_TENGBASE_KR_LP_COEFFICIENT_UPD_152_ADDR  0x08000098

#define PMD_IEEE9BLK_TENGBASE_KR_LP_STATUS_REPORT_REG_153_NAME "PMD_IEEE9BLK_TENGBASE_KR_LP_STATUS_REPORT_REG_153"
#define PMD_IEEE9BLK_TENGBASE_KR_LP_STATUS_REPORT_REG_153_ADDR  0x08000099

#define PMD_IEEE9BLK_TENGBASE_KR_LD_COEFFICIENT_UPD_154_NAME "PMD_IEEE9BLK_TENGBASE_KR_LD_COEFFICIENT_UPD_154"
#define PMD_IEEE9BLK_TENGBASE_KR_LD_COEFFICIENT_UPD_154_ADDR  0x0800009a

#define PMD_IEEE9BLK_TENGBASE_KR_LD_STATUS_REPORT_REG_155_NAME "PMD_IEEE9BLK_TENGBASE_KR_LD_STATUS_REPORT_REG_155"
#define PMD_IEEE9BLK_TENGBASE_KR_LD_STATUS_REPORT_REG_155_ADDR  0x0800009b

#define PMD_IEEE10BLK_PMD_KX_CONTROL_NAME "PMD_IEEE10BLK_PMD_KX_CONTROL"
#define PMD_IEEE10BLK_PMD_KX_CONTROL_ADDR  0x080000a0

#define PMD_IEEE10BLK_PMD_KX_STATUS_NAME "PMD_IEEE10BLK_PMD_KX_STATUS"
#define PMD_IEEE10BLK_PMD_KX_STATUS_ADDR  0x080000a1

#define PMD_IEEE10BLK_PMD_FECABILITY_NAME "PMD_IEEE10BLK_PMD_FECABILITY"
#define PMD_IEEE10BLK_PMD_FECABILITY_ADDR  0x080000aa

#define PMD_IEEE10BLK_PMD_FECCONTROL_NAME "PMD_IEEE10BLK_PMD_FECCONTROL"
#define PMD_IEEE10BLK_PMD_FECCONTROL_ADDR  0x080000ab

#define PMD_IEEE10BLK_PMD_CORRECTEDBLKSL_NAME "PMD_IEEE10BLK_PMD_CORRECTEDBLKSL"
#define PMD_IEEE10BLK_PMD_CORRECTEDBLKSL_ADDR  0x080000ac

#define PMD_IEEE10BLK_PMD_CORRECTEDBLKSH_NAME "PMD_IEEE10BLK_PMD_CORRECTEDBLKSH"
#define PMD_IEEE10BLK_PMD_CORRECTEDBLKSH_ADDR  0x080000ad

#define PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSL_NAME "PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSL"
#define PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSL_ADDR  0x080000ae

#define PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSH_NAME "PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSH"
#define PMD_IEEE10BLK_PMD_UNCORRECTEDBLKSH_ADDR  0x080000af

#define PCS_IEEE0BLK_PCS_IEEECONTROL1_NAME "PCS_IEEE0BLK_PCS_IEEECONTROL1"
#define PCS_IEEE0BLK_PCS_IEEECONTROL1_ADDR  0x18000000

#define PCS_IEEE0BLK_PCS_IEEESTATUS1_NAME "PCS_IEEE0BLK_PCS_IEEESTATUS1"
#define PCS_IEEE0BLK_PCS_IEEESTATUS1_ADDR  0x18000001

#define PCS_IEEE0BLK_PCS_IEEECONTROL2_NAME "PCS_IEEE0BLK_PCS_IEEECONTROL2"
#define PCS_IEEE0BLK_PCS_IEEECONTROL2_ADDR  0x18000007

#define PCS_IEEE0BLK_PCS_IEEESTATUS2_NAME "PCS_IEEE0BLK_PCS_IEEESTATUS2"
#define PCS_IEEE0BLK_PCS_IEEESTATUS2_ADDR  0x18000008

#define PCS_IEEE1BLK_PCS_LANESTATUS_NAME "PCS_IEEE1BLK_PCS_LANESTATUS"
#define PCS_IEEE1BLK_PCS_LANESTATUS_ADDR  0x18000018

#define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_NAME "PCS_IEEE1BLK_PCS_IEEETESTCONTROL"
#define PCS_IEEE1BLK_PCS_IEEETESTCONTROL_ADDR  0x18000019

#define PCS_IEEE2BLK_PCS_STATUS1_NAME "PCS_IEEE2BLK_PCS_STATUS1"
#define PCS_IEEE2BLK_PCS_STATUS1_ADDR  0x18000020

#define PCS_IEEE2BLK_PCS_STATUS2_NAME "PCS_IEEE2BLK_PCS_STATUS2"
#define PCS_IEEE2BLK_PCS_STATUS2_ADDR  0x18000021

#define PCS_IEEE2BLK_PCS_SEEDA0_NAME "PCS_IEEE2BLK_PCS_SEEDA0"
#define PCS_IEEE2BLK_PCS_SEEDA0_ADDR  0x18000022

#define PCS_IEEE2BLK_PCS_SEEDA1_NAME "PCS_IEEE2BLK_PCS_SEEDA1"
#define PCS_IEEE2BLK_PCS_SEEDA1_ADDR  0x18000023

#define PCS_IEEE2BLK_PCS_SEEDA2_NAME "PCS_IEEE2BLK_PCS_SEEDA2"
#define PCS_IEEE2BLK_PCS_SEEDA2_ADDR  0x18000024

#define PCS_IEEE2BLK_PCS_SEEDA3_NAME "PCS_IEEE2BLK_PCS_SEEDA3"
#define PCS_IEEE2BLK_PCS_SEEDA3_ADDR  0x18000025

#define PCS_IEEE2BLK_PCS_SEEDB0_NAME "PCS_IEEE2BLK_PCS_SEEDB0"
#define PCS_IEEE2BLK_PCS_SEEDB0_ADDR  0x18000026

#define PCS_IEEE2BLK_PCS_SEEDB1_NAME "PCS_IEEE2BLK_PCS_SEEDB1"
#define PCS_IEEE2BLK_PCS_SEEDB1_ADDR  0x18000027

#define PCS_IEEE2BLK_PCS_SEEDB2_NAME "PCS_IEEE2BLK_PCS_SEEDB2"
#define PCS_IEEE2BLK_PCS_SEEDB2_ADDR  0x18000028

#define PCS_IEEE2BLK_PCS_SEEDB3_NAME "PCS_IEEE2BLK_PCS_SEEDB3"
#define PCS_IEEE2BLK_PCS_SEEDB3_ADDR  0x18000029

#define PCS_IEEE2BLK_PCS_TPCONTROL_NAME "PCS_IEEE2BLK_PCS_TPCONTROL"
#define PCS_IEEE2BLK_PCS_TPCONTROL_ADDR  0x1800002a

#define PCS_IEEE2BLK_PCS_TPERRCOUNTER_NAME "PCS_IEEE2BLK_PCS_TPERRCOUNTER"
#define PCS_IEEE2BLK_PCS_TPERRCOUNTER_ADDR  0x1800002b

#define PHY_IEEE0BLK_PHY_IEEECONTROL1_NAME "PHY_IEEE0BLK_PHY_IEEECONTROL1"
#define PHY_IEEE0BLK_PHY_IEEECONTROL1_ADDR  0x20000000

#define PHY_IEEE0BLK_PHY_IEEESTATUS1_NAME "PHY_IEEE0BLK_PHY_IEEESTATUS1"
#define PHY_IEEE0BLK_PHY_IEEESTATUS1_ADDR  0x20000001

#define PHY_IEEE0BLK_PHY_IEEEID1_NAME "PHY_IEEE0BLK_PHY_IEEEID1"
#define PHY_IEEE0BLK_PHY_IEEEID1_ADDR  0x20000002

#define PHY_IEEE0BLK_PHY_IEEEID2_NAME "PHY_IEEE0BLK_PHY_IEEEID2"
#define PHY_IEEE0BLK_PHY_IEEEID2_ADDR  0x20000003

#define PHY_IEEE0BLK_PHY_IEEESPEEDABILITY_NAME "PHY_IEEE0BLK_PHY_IEEESPEEDABILITY"
#define PHY_IEEE0BLK_PHY_IEEESPEEDABILITY_ADDR  0x20000004

#define PHY_IEEE0BLK_PHY_IEEEDEVINPKG2_NAME "PHY_IEEE0BLK_PHY_IEEEDEVINPKG2"
#define PHY_IEEE0BLK_PHY_IEEEDEVINPKG2_ADDR  0x20000005

#define PHY_IEEE0BLK_PHY_IEEEDEVINPKG1_NAME "PHY_IEEE0BLK_PHY_IEEEDEVINPKG1"
#define PHY_IEEE0BLK_PHY_IEEEDEVINPKG1_ADDR  0x20000006

#define PHY_IEEE0BLK_PHY_IEEESTATUS2_NAME "PHY_IEEE0BLK_PHY_IEEESTATUS2"
#define PHY_IEEE0BLK_PHY_IEEESTATUS2_ADDR  0x20000008

#define PHY_IEEE1BLK_PHY_LANESTATUS_NAME "PHY_IEEE1BLK_PHY_LANESTATUS"
#define PHY_IEEE1BLK_PHY_LANESTATUS_ADDR  0x20000018

#define PHY_IEEE1BLK_PHY_IEEETESTCONTROL_NAME "PHY_IEEE1BLK_PHY_IEEETESTCONTROL"
#define PHY_IEEE1BLK_PHY_IEEETESTCONTROL_ADDR  0x20000019

#define DTE_IEEE0BLK_DTE_IEEECONTROL1_NAME "DTE_IEEE0BLK_DTE_IEEECONTROL1"
#define DTE_IEEE0BLK_DTE_IEEECONTROL1_ADDR  0x28000000

#define DTE_IEEE0BLK_DTE_IEEESTATUS1_NAME "DTE_IEEE0BLK_DTE_IEEESTATUS1"
#define DTE_IEEE0BLK_DTE_IEEESTATUS1_ADDR  0x28000001

#define DTE_IEEE0BLK_DTE_IEEEID1_NAME "DTE_IEEE0BLK_DTE_IEEEID1"
#define DTE_IEEE0BLK_DTE_IEEEID1_ADDR  0x28000002

#define DTE_IEEE0BLK_DTE_IEEEID2_NAME "DTE_IEEE0BLK_DTE_IEEEID2"
#define DTE_IEEE0BLK_DTE_IEEEID2_ADDR  0x28000003

#define DTE_IEEE0BLK_DTE_IEEESPEEDABILITY_NAME "DTE_IEEE0BLK_DTE_IEEESPEEDABILITY"
#define DTE_IEEE0BLK_DTE_IEEESPEEDABILITY_ADDR  0x28000004

#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_NAME "DTE_IEEE0BLK_DTE_IEEEDEVINPKG2"
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_ADDR  0x28000005

#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_NAME "DTE_IEEE0BLK_DTE_IEEEDEVINPKG1"
#define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_ADDR  0x28000006

#define DTE_IEEE0BLK_DTE_IEEESTATUS2_NAME "DTE_IEEE0BLK_DTE_IEEESTATUS2"
#define DTE_IEEE0BLK_DTE_IEEESTATUS2_ADDR  0x28000008

#define DTE_IEEE1BLK_DTE_LANESTATUS_NAME "DTE_IEEE1BLK_DTE_LANESTATUS"
#define DTE_IEEE1BLK_DTE_LANESTATUS_ADDR  0x28000018

#define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_NAME "DTE_IEEE1BLK_DTE_IEEETESTCONTROL"
#define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_ADDR  0x28000019

#define AN_IEEE0BLK_AN_IEEECONTROL1_NAME "AN_IEEE0BLK_AN_IEEECONTROL1"
#define AN_IEEE0BLK_AN_IEEECONTROL1_ADDR  0x38000000

#define AN_IEEE0BLK_AN_IEEESTATUS1_NAME "AN_IEEE0BLK_AN_IEEESTATUS1"
#define AN_IEEE0BLK_AN_IEEESTATUS1_ADDR  0x38000001

#define AN_IEEE0BLK_AN_IEEEID1_NAME "AN_IEEE0BLK_AN_IEEEID1"
#define AN_IEEE0BLK_AN_IEEEID1_ADDR  0x38000002

#define AN_IEEE0BLK_AN_IEEEID2_NAME "AN_IEEE0BLK_AN_IEEEID2"
#define AN_IEEE0BLK_AN_IEEEID2_ADDR  0x38000003

#define AN_IEEE0BLK_AN_IEEEDEVINPKG2_NAME "AN_IEEE0BLK_AN_IEEEDEVINPKG2"
#define AN_IEEE0BLK_AN_IEEEDEVINPKG2_ADDR  0x38000005

#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_NAME "AN_IEEE0BLK_AN_IEEEDEVINPKG1"
#define AN_IEEE0BLK_AN_IEEEDEVINPKG1_ADDR  0x38000006

#define AN_IEEE1BLK_AN_ADVERTISEMENT0_NAME "AN_IEEE1BLK_AN_ADVERTISEMENT0"
#define AN_IEEE1BLK_AN_ADVERTISEMENT0_ADDR  0x38000010

#define AN_IEEE1BLK_AN_ADVERTISEMENT1_NAME "AN_IEEE1BLK_AN_ADVERTISEMENT1"
#define AN_IEEE1BLK_AN_ADVERTISEMENT1_ADDR  0x38000011

#define AN_IEEE1BLK_AN_ADVERTISEMENT2_NAME "AN_IEEE1BLK_AN_ADVERTISEMENT2"
#define AN_IEEE1BLK_AN_ADVERTISEMENT2_ADDR  0x38000012

#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_NAME "AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0"
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ADDR  0x38000013

#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1_NAME "AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1"
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1_ADDR  0x38000014

#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2_NAME "AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2"
#define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY2_ADDR  0x38000015

#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_NAME "AN_IEEE1BLK_AN_XNP_TRANSMIT0"
#define AN_IEEE1BLK_AN_XNP_TRANSMIT0_ADDR  0x38000016

#define AN_IEEE1BLK_AN_XNP_TRANSMIT1_NAME "AN_IEEE1BLK_AN_XNP_TRANSMIT1"
#define AN_IEEE1BLK_AN_XNP_TRANSMIT1_ADDR  0x38000017

#define AN_IEEE1BLK_AN_XNP_TRANSMIT2_NAME "AN_IEEE1BLK_AN_XNP_TRANSMIT2"
#define AN_IEEE1BLK_AN_XNP_TRANSMIT2_ADDR  0x38000018

#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_NAME "AN_IEEE1BLK_AN_LP_XNP_ABILITY0"
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_ADDR  0x38000019

#define AN_IEEE1BLK_AN_LP_XNP_ABILITY1_NAME "AN_IEEE1BLK_AN_LP_XNP_ABILITY1"
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY1_ADDR  0x3800001a

#define AN_IEEE1BLK_AN_LP_XNP_ABILITY2_NAME "AN_IEEE1BLK_AN_LP_XNP_ABILITY2"
#define AN_IEEE1BLK_AN_LP_XNP_ABILITY2_ADDR  0x3800001b

#define AN_IEEE3BLK_AN_BPSTATUS_NAME "AN_IEEE3BLK_AN_BPSTATUS"
#define AN_IEEE3BLK_AN_BPSTATUS_ADDR  0x38000030

#define AN_IEEE3BLK_EEE_ADV_NAME "AN_IEEE3BLK_EEE_ADV"
#define AN_IEEE3BLK_EEE_ADV_ADDR  0x3800003c

#define AN_IEEE3BLK_EEE_LP_ADV_NAME "AN_IEEE3BLK_EEE_LP_ADV"
#define AN_IEEE3BLK_EEE_LP_ADV_ADDR  0x3800003d

#endif
