/* bone_shiftout - copyright (C) 2016 Nash Kaminski
 * Portions of file copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
 *
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *	* Redistributions of source code must retain the above copyright
 *		notice, this list of conditions and the following disclaimer.
 *
 *	* Redistributions in binary form must reproduce the above copyright
 *		notice, this list of conditions and the following disclaimer in the
 *		documentation and/or other materials provided with the
 *		distribution.
 *
 *	* Neither the name of Texas Instruments Incorporated nor the names of
 *		its contributors may be used to endorse or promote products derived
 *		from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <pru_cfg.h>
#include <pru_intc.h>
#include <rsc_types.h>
#include <pru_rpmsg.h>
#include "registers.h"
#include "commands.h"
#include "shiftreg_pru.h"
#include "resource_table_0.h"

/* Host-0 Interrupt sets bit 30 in register R31 */
#define HOST_INT			((uint32_t) 1 << 30)

/* The PRU-ICSS system events used for RPMsg are defined in the Linux device tree
 * PRU0 uses system event 16 (To ARM) and 17 (From ARM)
 * PRU1 uses system event 18 (To ARM) and 19 (From ARM)
 */
#define TO_ARM_HOST			16
#define FROM_ARM_HOST			17

/*
 * Using the name 'rpmsg-pru' will probe the rpmsg_pru driver found
 * at linux-x.y.z/drivers/rpmsg/rpmsg_pru.c
 */
#define CHAN_NAME			"rpmsg-pru"
#define CHAN_DESC			"Channel 30"
#define CHAN_PORT			30

/*
 * Used to make sure the Linux drivers are ready for RPMsg communication
 * Found at linux-x.y.z/include/uapi/linux/virtio_config.h
 */
#define VIRTIO_CONFIG_S_DRIVER_OK	4

uint8_t payload[RPMSG_BUF_SIZE];

/* Shift register output types */
shiftreg_t reg;
unsigned char itercounter;

/* Danger! Keep global since these are larger than the stack! */
char ser0_buf[MAX_BITS];
char ser1_buf[MAX_BITS];
char ser2_buf[MAX_BITS];
	
/*
 * main.c
 */
void main(void)
{
	/* Control messaging types */
	struct pru_rpmsg_transport transport;
	uint16_t src, dst, len;
	volatile uint8_t *status;
	char rstatus; 
	/* Allow OCP master port access by the PRU so the PRU can read external memories */
	CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;

	/* Clear the status of the PRU-ICSS system event that the ARM will use to 'kick' us */
	CT_INTC.SICR_bit.STS_CLR_IDX = FROM_ARM_HOST;

	/* Make sure the Linux drivers are ready for RPMsg communication */
	status = &resourceTable.rpmsg_vdev.status;
	while (!(*status & VIRTIO_CONFIG_S_DRIVER_OK));

	/* Initialize the RPMsg transport structure */
	pru_rpmsg_init(&transport, &resourceTable.rpmsg_vring0, &resourceTable.rpmsg_vring1, TO_ARM_HOST, FROM_ARM_HOST);

	/* Create the RPMsg channel between the PRU and ARM user space using the transport structure. */
	while (pru_rpmsg_channel(RPMSG_NS_CREATE, &transport, CHAN_NAME, CHAN_DESC, CHAN_PORT) != PRU_RPMSG_SUCCESS);

	/* Initilaize the shift register output subsystem */
	itercounter=0;
	reg.ser0 = 0;
	reg.ser1 = 4;
	reg.ser2 = 5;
	reg.serclk = 1;
	reg.latch = 2;
	reg.clear = 3;
	reg.nbits = 8;
	memset(ser0_buf,0x00,MAX_BITS);
	memset(ser1_buf,0x00,MAX_BITS);
	memset(ser2_buf,0x00,MAX_BITS);
	shiftreg_clear(&reg);
	while (1) {
		/* shift register output */
		shiftreg_iterate(&reg, ser0_buf, ser1_buf, ser2_buf, itercounter);
		itercounter++;
		if(itercounter > 127){
			itercounter=1;
		}
		/* Control message handling */
		/* Check bit 30 of register R31 to see if the ARM has kicked us */
		if (__R31 & HOST_INT) {
			/* Clear the event status */
			CT_INTC.SICR_bit.STS_CLR_IDX = FROM_ARM_HOST;
			/* Receive all available messages, multiple messages can be sent per kick */
			while (pru_rpmsg_receive(&transport, &src, &dst, payload, &len) == PRU_RPMSG_SUCCESS) {
				/* handle incoming control messages */
				rstatus = 0;
				if(len != 3){
					continue;
				}
				/* Switch based on opcode and return the opcode if successful, 0x00 if not */
				switch(payload[0]){
					case SET_PWM0:
						if(payload[1] < MAX_BITS){
							ser0_buf[payload[1]] = payload[2];
							rstatus = SET_PWM0;	
						}
						break;
					case SET_PWM1:
						if(payload[1] < MAX_BITS){
							ser1_buf[payload[1]] = payload[2];
							rstatus = SET_PWM1;	
						}
						break;
					case SET_PWM2:
						if(payload[1] < MAX_BITS){
							ser2_buf[payload[1]] = payload[2];
							rstatus = SET_PWM2;	
						}
						break;
					case SET_NBITS:
						if(*((uint16_t *)(payload+1)) <= MAX_BITS){
							reg.nbits = *((uint16_t *)(payload+1));
							rstatus = SET_NBITS;
						}
						break;
					case SET_PWM_ALL:
						memset(ser0_buf,payload[2],MAX_BITS);
						memset(ser1_buf,payload[2],MAX_BITS);
						memset(ser2_buf,payload[2],MAX_BITS);
						break;												
				}

				/* Currently unnecessary
				 * pru_rpmsg_send(&transport, dst, src, &rstatus, 1); */
			}
		}
	}
}
