system/apu/index.js
function( address, value ) {
		if ( address < 0x4 ) {
			// pulse 1 registers
			this.pulse1.writeRegister( address, value );
		} else if ( address < 0x8 ) {
			// pulse 2 registers
			this.pulse2.writeRegister( address - 0x4, value );
		} else if ( address < 0xc ) {
			// triangle registers
			this.triangle.writeRegister( address - 0x8, value );
		} else if ( address < 0x10 ) {
			// noise registers
			this.noise.writeRegister( address - 0xc, value );
		} else if ( address < 0x14 ) {
			// DMC registers
			this.dmc.writeRegister( address - 0x10, value );
		} else if ( address === 0x15 ) {
			// enabling / disabling channels
			this.writeStatus( value );
		} else if ( address === 0x17 ) {
			// set framecounter mode

			this.frameCounterMode = +!!(value & 0x80);
			this.frameCounterInterrupt = !( value & 0x40 );

			this.cycles = 0;
			// TODO:
			// If the write occurs during an APU cycle, the effects occur 3 CPU cycles
			// after the $4017 write cycle, and if the write occurs between APU cycles,
			// the effects occurs 4 CPU cycles after the write cycle.

			if ( this.frameCounterMode ) {
				// Writing to $4017 with bit 7 set will immediately generate a clock for
				// both the quarter frame and the half frame units, regardless of what
				// the sequencer is doing.

				this.doQuarterFrame();
				this.doHalfFrame();
			}

		}
	}
function( address, value ) {
		if ( address < 0x4 ) {
			// pulse 1 registers
			this.pulse1.writeRegister( address, value );
		} else if ( address < 0x8 ) {
			// pulse 2 registers
			this.pulse2.writeRegister( address - 0x4, value );
		} else if ( address < 0xc ) {
			// triangle registers
			this.triangle.writeRegister( address - 0x8, value );
		} else if ( address < 0x10 ) {
			// noise registers
			this.noise.writeRegister( address - 0xc, value );
		} else if ( address < 0x14 ) {
			// DMC registers
			this.dmc.writeRegister( address - 0x10, value );
		} else if ( address === 0x15 ) {
			// enabling / disabling channels
			this.writeStatus( value );
		} else if ( address === 0x17 ) {
			// set framecounter mode

			this.frameCounterMode = +!!(value & 0x80);
			this.frameCounterInterrupt = !( value & 0x40 );

			this.cycles = 0;
			// TODO:
			// If the write occurs during an APU cycle, the effects occur 3 CPU cycles
			// after the $4017 write cycle, and if the write occurs between APU cycles,
			// the effects occurs 4 CPU cycles after the write cycle.

			if ( this.frameCounterMode ) {
				// Writing to $4017 with bit 7 set will immediately generate a clock for
				// both the quarter frame and the half frame units, regardless of what
				// the sequencer is doing.

				this.doQuarterFrame();
				this.doHalfFrame();
			}

		}
	}
function ( address , value ) { if ( address < 0x4 ) { // pulse 1 registers this . pulse1 . writeRegister ( address , value ) ; } else if ( address < 0x8 ) { // pulse 2 registers this . pulse2 . writeRegister ( address - 0x4 , value ) ; } else if ( address < 0xc ) { // triangle registers this . triangle . writeRegister ( address - 0x8 , value ) ; } else if ( address < 0x10 ) { // noise registers this . noise . writeRegister ( address - 0xc , value ) ; } else if ( address < 0x14 ) { // DMC registers this . dmc . writeRegister ( address - 0x10 , value ) ; } else if ( address === 0x15 ) { // enabling / disabling channels this . writeStatus ( value ) ; } else if ( address === 0x17 ) { // set framecounter mode this . frameCounterMode = + ! ! ( value & 0x80 ) ; this . frameCounterInterrupt = ! ( value & 0x40 ) ; this . cycles = 0 ; // TODO: // If the write occurs during an APU cycle, the effects occur 3 CPU cycles // after the $4017 write cycle, and if the write occurs between APU cycles, // the effects occurs 4 CPU cycles after the write cycle. if ( this . frameCounterMode ) { // Writing to $4017 with bit 7 set will immediately generate a clock for // both the quarter frame and the half frame units, regardless of what // the sequencer is doing. this . doQuarterFrame ( ) ; this . doHalfFrame ( ) ; } } }
Write to APU registers.
Write to APU registers .